CMOS anti-fuse cell
AssigneeNEO Semiconductor, Inc.
InventorFu-Chang Hsu
Life of this patent
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Abstract
A CMOS anti-fuse cell is disclosed. In one aspect, an apparatus includes an N− well and an anti-fuse cell formed on the N− well. The anti-fuse cell includes a drain P+ diffusion deposited in the N− well, a source P+ diffusion deposited in the N− well, and an oxide layer deposited on the N− well and having an overlapping region that overlaps the drain P+ diffusion. A control gate is deposited on the oxide layer. A data bit of the anti-fuse cell is programmed when a voltage difference between the control gate and the drain P+ diffusion exceeds a voltage threshold of the oxide layer and forms a leakage path from the control gate to the drain P+ diffusion. The leakage path is confined to occur in the overlapping region.
Claims20
An apparatus, comprising:
- an N-well;
- and
- an anti-fuse cell formed on the N-well, wherein the anti-fuse cell includes a drain P+ diffusion deposited in the N-well, a source P+ diffusion deposited in the N-well, an oxide layer deposited on the N-well and having an overlapping region that overlaps a portion of the drain P+ diffusion and a portion of a control gate deposited on the oxide layer for facilitating anti-fuse programming, wherein a bit of the anti-fuse cell is programmed when a voltage difference between the control gate and the drain P+ diffusion exceeds a voltage threshold of the oxide layer and forms a leakage path from the control gate to the drain P+ diffusion, and wherein the leakage path is confined to occur in the overlapping region.
A method of operating an anti-fuse cell comprising a drain P+ diffusion deposited in an N-well, a source P+ diffusion deposited in the N-well, an oxide layer deposited on the N-well, a control gate deposited over the oxide layer and having a first overlapping region generated by extending a portion of the drain P+ diffusion to a portion of the control gate separated by a portion of the oxide layer for facilitating anti-fuse programming, and a second overlapping region that overlaps the source P+ diffusion, the method comprising:
- applying a first voltage to the control gate to turn off a channel region of the anti-fuse cell;
- and
- applying a second voltage to the drain P+ diffusion wherein a first bit of the anti-fuse cell is programmed when a voltage difference between the first and second voltages exceeds a voltage threshold of the oxide layer and forms a leakage path from the control gate to the drain P+ diffusion, and wherein the leakage path is confined to occur in the first overlapping region.
A method of operating an anti-fuse cell comprising a drain N− diffusion deposited in an P+ well, a source N− diffusion deposited in the P+ well, an oxide layer deposited on the P+ well, a control gate deposited on the oxide layer and having a first overlapping region generated by extending a portion of the drain N− diffusion into a portion of the control gate separated by a portion of the oxide layer for facilitating anti-fuse programming, and a second overlapping region that overlaps the source N− diffusion, the method comprising:
- applying a first voltage to the control gate to turn off a channel region of the anti-fuse cell;
- and
- applying a second voltage to the drain N-diffusion wherein a first bit of the anti-fuse cell is programmed when a voltage difference between the first and second voltages exceeds a voltage threshold of the oxide layer and forms a leakage path from the control gate to the drain N− diffusion, and wherein the leakage path is confined to occur in the first overlapping region.
Dependencies are inferred from the claim text.