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US 9,792,994 B1Granted
Bulk modulation scheme to reduce I/O pin capacitance
AssigneeSanDisk Technologies LLC
InventorsPrimit Modi, Venkatesh Ramachandra
Life of this patent
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Abstract
A driver circuit, such as could be used as an off-chip driver for an I/O pin on a memory circuit, is presented. The driver has a PMOS connected between a supply level and the driver's output node. In an active mode, the bulk terminal of the PMOS is connected to the supply level; and in a standby mode, the PMOS's bulk terminal is set to a higher level. This reduces the leakage current through the PMOS in the standby mode, allowing for smaller device with a lower capacitance to be used.
Claims18
A driver circuit, comprising:
- a first PMOS transistor connected between a first supply voltage and an intermediate node and having a control gate connected to receive an input signal;
- a first NMOS transistor connected between the intermediate node and ground and having a control gate connected to receive the input signal, wherein an output of the driver circuit is provided from the intermediate node;
- and
- a bulk biasing circuit connected to a body terminal of the first PMOS transistor and connected to receive a mode enable signal, wherein when the mode enable signal is asserted the bulk biasing circuit biases the body terminal to the first supply voltage and when the mode enable signal is de-asserted the bulk biasing circuit biases the body terminal to a voltage greater than the first supply voltage;
- wherein the driver circuit is formed on a non-volatile memory circuit, wherein the output of the driver circuit is connected to drive an input/output pin of the non-volatile memory circuit, wherein the mode enable signal is an enable signal for the non-volatile memory circuit, and wherein the input/output pin is further connected to the first supply voltage through a first diode and connected to ground through a second diode.
2 more elements
A non-volatile memory circuit, comprising:
- a chip enable pin connectable to receive a chip enable signal;
- an input-output pin connectable to provide an output signal;
- and
- a driver circuit connected to receive the chip enable signal and receive a first on-chip signal, the driver circuit including:
- a first PMOS transistor connected between a first on-chip supply voltage and an intermediate node and having a control gate connected to receive the first on-chip signal, the intermediate node connected to the input-output pin;
- a first NMOS transistor connected between the intermediate node and ground and having a control gate connected to receive the first on-chip signal;
- and
- a bulk biasing circuit connected to a body terminal of the first PMOS transistor and connected to receive the chip enable signal, wherein when the chip enable signal is asserted the bulk biasing circuit biases the body terminal to the first supply voltage and when the chip enable signal is de-asserted the bulk biasing circuit biases the body terminal to a voltage greater than the first supply voltage,
- wherein the driver circuit is formed on a non-volatile memory circuit, wherein the output of the driver circuit is connected to drive an input/output pin of the non-volatile memory circuit, wherein the chip enable signal is an enable signal for the non-volatile memory circuit, and wherein the input/output pin is further connected to the first supply voltage through a first diode and connected to ground through a second diode.
6 more elements
A method, comprising:
- supplying a driver circuit with a first supply voltage, the driver circuit including:
- a first PMOS transistor connected between the first supply voltage and an intermediate node and having a control gate connected to receive an input signal;
- and
- a first NMOS transistor connected between the intermediate node and ground and having a control gate connected to receive an input signal, wherein an output of the driver is provided from the intermediate node;
- and
- in response to an enable signal, operating the driver circuit in either an active mode, in which a body terminal of the first PMOS is biased to the first supply voltage, or a standby mode, in which the body terminal of the first PMOS is biased to a voltage greater than the first supply voltage,
- wherein the driver circuit is formed on a non-volatile memory circuit, wherein the output of the driver is connected to drive an input/output pin of the memory circuit, wherein the driver circuit is operated in the active mode when a chip enable signal for the memory circuit is asserted and operated in the standby mode when the chip enable signal for the memory circuit is de-asserted, and wherein the input/output pin is further connected to the first supply voltage through a first diode and connected to ground through a second diode.
4 more elements
Dependencies are inferred from the claim text.