Semiconductor memory device and method of manufacturing the same
AssigneeToshiba Memory Corporation
InventorsShuichi Toriyama, Hideto Horii, Tomoya Kawai
Life of this patent
Estimating the term…
Abstract
In a write operation to memory cells, the control unit is operative to, when a threshold voltage to be provided to a selected memory cell is not less than a reference value, apply a program voltage to a word line corresponding to a selected memory cell, and cause a voltage applied to a first word line corresponding to a first non-selected memory cell positioned between the first end and the selected memory cell to be higher than a voltage applied to a second word line corresponding to a second non-selected memory cell positioned between the second end and the selected memory cell.
Claims16
A semiconductor memory device, comprising:
- a memory cell array in which a plurality of memory cells are connected in series to form a memory unit;
- word lines connected to control gates of the plurality of memory cells;
- a bit line connected to a first end of the memory unit;
- a source line connected to a second end of the memory unit;
- and
- a control unit that controls the memory cell array, wherein
- in a write operation to the memory cells, the control unit is operative to, when a threshold voltage to be provided to a selected memory cell is not less than a reference value,
- apply a program voltage to a word line corresponding to a selected memory cell, and
- cause a voltage applied to a first word line corresponding to a first non-selected memory cell positioned between the first end and the selected memory cell to be higher than a voltage applied to a second word line corresponding to a second non-selected memory cell positioned between the second end and the selected memory cell.
A method of controlling a semiconductor memory device, the semiconductor memory device comprising:
- a memory cell array in which a plurality of memory cells are connected in series to form a memory unit;
- word lines connected to control gates of the plurality of memory cells;
- a bit line connected to a first end of the memory unit;
- and a source line connected to a second end of the memory unit,
- wherein in a write operation to the memory cells, the method includes, when a threshold voltage to be provided to a selected memory cell is not less than a reference value,
- applying a program voltage to a word line corresponding to a selected memory cell, and
- causing a voltage applied to a first word line corresponding to a first non-selected memory cell positioned between the first end and the selected memory cell to be equal to a voltage applied to a second word line corresponding to a second non-selected memory cell positioned between the second end and the selected memory cell.
Dependencies are inferred from the claim text.