Flash memory system and word line interleaving method thereof
AssigneeSamsung Electronics Co., Ltd.
InventorsYongjune Kim, Hong Rak Son, Seonghyeog Choi, Junjin Kong
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Abstract
Provided are a flash memory system and a word line interleaving method thereof. The flash memory system includes a memory cell array, and a word line interleaving logic. The memory cell array is connected to a plurality of word lines. The word line (WL) interleaving logic performs an interleaving operation on WL data corresponding to at least two different wordlines and programming data, including the interleaved data, to the memory cell array.
Claims14
A method of operating a memory device having a three-dimensional cell array on a substrate, the method comprising:
- performing an error correction code (ECC) encoding on data for at least two different wordlines to generate parity bits, the at least two different wordlines coupled to a plurality of memory cells stacked on the substrate in a stacking direction;
- interleaving the data for the at least two different wordlines by mixing the generated parity bits and the data for the at least two different wordlines, the plurality of memory cells having a bit error rate imbalance in accordance with a physical height of the wordlines along the stacking direction of the stacked memory cells, the interleaving correcting for the bit error rate imbalance;
- and
- programming data, including the interleaved data, to the three-dimensional cell array.
A method of operating a memory device having a three-dimensional cell array on a substrate, the method comprising:
- performing an error correction code (ECC) encoding on data for at least two different wordlines to generate parity bits, the at least two different wordlines coupled to a plurality of memory cells stacked on the substrate in a stacking direction;
- interleaving the data for the at least two different wordlines by mixing the generated parity bits and the data for the at least two different wordlines, the plurality of memory cells having a bit error rate imbalance according a physical location of wordlines within the stacked memory cells, each wordline being coupled to the plurality of memory cells along a direction orthogonal to the stacking direction of the stacked memory cells, the interleaving correcting for the bit error rate imbalance;
- and
- programming data, including the interleaved data, to three-dimensional cell array.
Dependencies are inferred from the claim text.