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US 9,792,989 B2Granted
Memory system including nonvolatile memory
AssigneeToshiba Memory Corporation
InventorTatsuhiro Suzumura
Life of this patent
Estimating the term…
Abstract
According to one embodiment, a memory system includes a nonvolatile memory, a command managing unit, a command issuing unit, a data control unit and a command monitoring unit. The command issuing unit issues a command received by the command managing unit to the nonvolatile memory. The data control unit controls a reading or writing of data to the nonvolatile memory. The command monitoring unit monitors the command managing unit and outputs a receipt signal to the data control unit when the command managing unit receives the command. The data control unit interrupts the reading or writing when receiving the receipt signal, issues the command from the command issuing unit to the nonvolatile memory, and resumes the reading or writing after issuing the command.
Claims20
A memory system comprising:
- a nonvolatile memory configured to store data, the nonvolatile memory including a first memory and a second memory, the first memory including a first buffer and a first memory circuit, and the second memory including a second buffer and a second memory circuit;
- a command managing circuit configured to receive and manage a command;
- a command issuing circuit configured to issue the command received by the command managing circuit to the nonvolatile memory;
- a data control circuit configured to control, based on the command, an operation that is one of reading of data from the nonvolatile memory and writing of data to the nonvolatile memory;
- and
- a command monitoring circuit configured to monitor the command managing circuit and output a receipt signal to the data control circuit when the command managing circuit receives the command, wherein
- the data control circuit interrupts transferring of data between the data control circuit and the nonvolatile memory based on a first command when receiving the receipt signal as to a second command from the command monitoring circuit,
- the command issuing circuit issues the second command to the nonvolatile memory after the interruption of the transferring of data between the data control circuit and the nonvolatile memory based on the first command,
- the data control circuit resumes the transferring of data between the data control circuit and the nonvolatile memory based on the first command after the issuance of the second command, and
- transferring of data between the first buffer and the data control circuit based on the first command is simultaneously performed with transferring of data between the second buffer and the second memory circuit based on the second command, after the resumption of the transferring of data between the data control circuit and the nonvolatile memory based on the first command.
7 more elements
A memory system comprising:
- a nonvolatile memory configured to store data, the nonvolatile memory including a first memory, the first memory including a first buffer and a first memory circuit;
- and
- a controller configured to control the nonvolatile memory, the controller interrupting a first transferring of data between the controller and the first buffer, the first transferring being based on a first command, the controller issuing a second command to the nonvolatile memory, and then the controller resuming the first transferring of data between the controller and the first buffer, after the resumption of the first transferring, the first transferring of data between the controller and the first buffer being simultaneously performed with a second transferring of data between the first buffer and the first memory circuit, the second transferring being based on the second command.
A memory system comprising:
- a nonvolatile memory configured to store data, the nonvolatile memory including a first memory and a second memory, the first memory including a first buffer and a first memory circuit, the second memory including a second buffer and a second memory circuit;
- and
- a controller configured to control the nonvolatile memory, the controller interrupting a first transferring of data between the controller and the first buffer, the first transferring being based on a first command, the controller issuing a second command to the nonvolatile memory, and then the controller resuming the first transferring of data between the controller and the first buffer, after the resumption of the first transferring, the first transferring of data between the controller and the first buffer being simultaneously performed with a second transferring of data between the second buffer and the second memory circuit, the second transferring being based on the second command.
A memory system comprising:
- a nonvolatile memory configured to store data, the nonvolatile memory including a first memory, the first memory including a first buffer and a first memory circuit;
- and
- a controller configured to control the nonvolatile memory, during a first transferring of data being in progress between the first buffer and the first memory circuit, the first transferring being based on a first command, the controller issuing a second command to the nonvolatile memory, after the issue of the second command, a second transferring of data between the controller and the first buffer being simultaneously performed with a third transferring of data between the first buffer and the first memory circuit, the second transferring being based on the first command and the third transferring being based on the second command.
A memory system comprising:
- a nonvolatile memory con figured to store data, the nonvolatile memory including a first memory and a second memory, the first memory including a first buffer and a first memory circuit, the second memory including a second buffer and a second memory circuit;
- and
- a controller configured to control the nonvolatile memory, during a first transferring of data being in progress between the first buffer and the first memory circuit, the first transferring being based on a first command, the controller issuing a second command to the nonvolatile memory, after the issue of the second command, a second transferring of data between the controller and the first buffer being simultaneously performed with a third transferring of data between the second buffer and the second memory circuit, the second transferring being based on the first command and the third transferring is based on the second command.
Dependencies are inferred from the claim text.