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US 9,792,986 B2Granted
Phase change memory current
AssigneeIntel Corporation
InventorsMase J. Taub, Sandeep K. Guliani, Kiran Pangal, Raymond W. Zeng
Life of this patent
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Abstract
The present disclosure relates to phase change memory current. An apparatus includes a memory controller including a word line (WL) control module and a bit line (BL) control module, the memory controller is to initiate selection of a memory cell. The apparatus further includes a mitigation module to configure a first line selection logic to reduce a transient energy dissipation of the memory cell, the transient energy related to selecting the memory cell.
Claims18
An apparatus comprising:
- a memory controller comprising a word line (WL) control module and a bit line (BL) control module, the memory controller to initiate selection of a memory cell in a phase change memory;
- and
- a mitigation module to configure a first line selection logic to reduce transient energy dissipation related to snap back occurring when selecting the memory cell by:
- enabling a selection current source to provide a selection current greater than or equal to a hold current associated with the memory cell,
- configuring the first line selection logic to increase an allowable current to the memory cell by decreasing a drain-source resistance for at least one MOSFET in a current path and enable a pulse current source to provide a pulse current to at least one of read from or program the memory cell, and
- disabling the selection current source when the pulse current source is enabled.
3 more elements
A method comprising:
- initiating, by a memory controller, selection of a memory cell in a phase change memory;
- and
- configuring, by a mitigation module, a first line selection logic to reduce a transient energy dissipation of the memory cell, the transient energy related to snap back occurring when selecting the memory cell;
- enabling, by the mitigation module, a selection current source to provide a selection current, the selection current greater than or equal to a hold current associated with the memory cell;
- configuring, by the mitigation module, the first line selection logic to increase an allowable current to the memory cell by decreasing a drain-source resistance for at least one MOSFET in a current path;
- enabling, by the mitigation module, a pulse current source to provide a pulse current to the memory cell, the pulse current to at least one of read from or program the memory cell;
- and disabling, by the mitigation module, a selection current source when the pulse current source is enabled.
4 more elements
A system comprising:
- a processor;
- a cross-point memory array comprising a memory cell in a phase change memory, a word line (WL) and a bit line (BL), the memory cell coupled between the word line and the bit line;
- and
- a memory controller to initiate selection of a target memory cell, the memory controller comprising:
- a WL control module and a BL control module, and
- a mitigation module to configure a first line selection logic to reduce transient energy dissipation related to snap back occurring when selecting the memory cell by enabling a selection current source to provide a selection current greater than or equal to a hold current associated with the memory cell, configuring the first line selection logic to increase an allowable current to the memory cell by decreasing a drain-source resistance for at least one MOSFET in a current path and enable a pulse current source to provide a pulse current to at least one of read from or program the memory cell, and disabling the selection current source when the pulse current source is enabled.
3 more elements
Dependencies are inferred from the claim text.