Memory with read circuitry and method of operating
AssigneeNXP USA, Inc.
InventorsPerry H. Pelley, Frank K. Baker, Jr.
Life of this patent
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Abstract
A non-volatile memory includes a first bit cell having a programmable resistive element coupled to a write bit line wherein the programmable resistive element is programmable to one of two resistive states, a resistive element coupled to the programmable resistive element at a circuit node, and a first transistor configured to operate in saturation during a read operation. The first transistor has a control electrode coupled to the circuit node and a first current electrode coupled to a read bit line.
Claims20
A non-volatile memory comprising:
- a first bit cell having a programmable resistive element coupled to a write bit line wherein the programmable resistive element is programmable to one of two resistive states;
- a resistive element coupled to the programmable resistive element at a circuit node;
- and
- a first transistor configured to operate in saturation during a read operation and having a gate control electrode directly coupled to the circuit node and a first current electrode coupled to a read bit line.
A non-volatile memory, comprising:
- a first bit cell coupled a circuit node, wherein a state of the first bit cell affects voltage at the circuit node;
- a first transistor having a first current electrode coupled to the circuit node, a second current electrode, and a control electrode coupled to receive an isolation signal;
- a second transistor having a control electrode coupled to the second current electrode of the first transistor and a first current electrode coupled to a read bit line;
- and
- a Metal Oxide Semiconductor (MOS) capacitor having a first terminal coupled to the control electrode of the second transistor and a second terminal coupled to receive a boost signal, which, during a read operation, is configured to provide a boost voltage.
In a non-volatile memory, a method comprises:
- selecting a first bit cell having a programmable resistive element for a read operation wherein the programmable resistive element is programmable to one of two resistive states;
- during the read operation, operating a first transistor in saturation, wherein the first transistor has a gate control electrode directly coupled to a circuit node and a first current electrode coupled to a read bit line, and coupling the first bit cell to the circuit node, wherein the non-volatile memory includes a resistive element coupled to the circuit node;
- and
- sensing the read bit line to determine a state of the selected first bit cell.
Dependencies are inferred from the claim text.