Loading patent…
AssigneeKhalifa University of Science and Technology
InventorsBaker Shehadah Mohammad, Khaled Hamed Salah, Mahmoud Abdullah Al-Qutayri
Estimating the term…
The present invention provides an erasure circuitry, a method for erasing a volatile memory, a volatile memory and erasure module in the form of computer readable instructions, where the erasure circuitry is adapted to erase the memory at occurrence of a predefined event. The erasure circuitry includes a negative pulse generator which is adapted to reduce the charge on capacitor in one or more volatile memory cells to zero logic by using a switch connected to the Voltage Reference (Vref) of the volatile memory cell, a controller and a negative power supply. The switch and the negative power supply impose a negative pulse on the Vref of the volatile memory cells on being instructed by the controller at the occurrence of a predefined event. An erasure module associated with the controller is provided for instructing the erasure circuitry for erasing data at the occurrence of a predefined event.
An erasure circuitry for erasing a dynamic volatile memory comprising a plurality of dynamic memory cells, the erasure circuitry comprising a negative pulse generator adapted to generate a negative pulse for reducing Voltage Reference (Vref) of one or more of the dynamic volatile memory cells to zero logic at occurrence of a predefined event for discharging one or more capacitors related to said one or more of the dynamic volatile memory cells.
A method of erasing a dynamic volatile memory comprising a plurality of dynamic volatile memory cells, the method comprising imposing a negative pulse on Voltage reference (Vref) of one or more of the dynamic volatile memory cells to reduce the Vref of the one or more of the dynamic volatile memory cells to zero logic at occurrence of a predefined event for discharging one or more capacitors related to said one or more of the dynamic volatile memory cells.
A dynamic volatile memory comprising a plurality of dynamic volatile memory cells and a negative pulse generator adapted to generate a negative pulse for reducing Voltage reference (Vref) of one or more of the dynamic volatile memory cells to zero logic at occurrence of a predefined event for discharging one or more capacitors related to said one or more of the dynamic volatile memory cells.
The dynamic volatile memory as claimed in 22, wherein the dynamic volatile memory is connected to a processing unit accessible by multiple users, processes, applications or services and wherein the predefined event is before switching between a first user, process, application or service and a subsequent user, process, application or service such that any data stored inside the memory is erased by imposition of negative pulse on the Vref by activating the negative pulse generator.
Dependencies are inferred from the claim text.