Memory system including plurality of DRAM devices operating selectively
AssigneeSamsung Electronics Co., Ltd.
InventorsTaewoong Ha, Byungchul Ko, Daekyoung Kim, Jonghwan Kim
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Abstract
A memory system including a plurality of dynamic random access memory (DRAM) devices and a DRAM controller is provided. The plurality of DRAM devices includes one or more DRAM groups. Each of the one or more DRAM groups includes at least two DRAM devices. The DRAM controller outputs a clock enable signal, and controls a selection signal used to select a target DRAM device that operates in a normal mode in response to the clock enable signal. At least one target DRAM device is selected from the one or more DRAM groups. One or more stand-by DRAM devices other than the at least one target DRAM device operates in a self-refresh mode.
Claims20
A memory system comprising:
- a plurality of dynamic random access memory (DRAM) devices including one or more DRAM groups, each of the one or more DRAM groups including at least two DRAM devices;
- a plurality of stabilization circuits configured to provide a self-refresh signal to the plurality of DRAM devices;
- and
- a DRAM controller configured to:
- output a clock enable signal, and
- control a selection signal used to select at least one target DRAM device that operates in a normal mode in response to the clock enable signal, the at least one target DRAM device being selected from each one of the one or more DRAM groups,
- wherein at least one stand-by DRAM device other than the at least one target DRAM device operates in a self-refresh mode in response to the selection signal based on the self-refresh signal, when the at least one target DRAM device operates in the normal mode.
A memory system comprising:
- a plurality of dynamic random access memory (DRAM) devices including one or more DRAM groups, each of the one or more DRAM groups including at least two DRAM devices;
- a plurality of stabilization circuits configured to provide a self-refresh signal to the plurality of DRAM devices;
- and
- a DRAM controller configured to:
- output a clock enable signal, and
- control one or more selection signals, each of the one or more selection signals being used to select at least one target DRAM device that operates in a normal mode in response to the clock enable signal, the at least target DRAM device being selected from a corresponding one of the one or more DRAM groups,
- wherein at least one stand-by DRAM device other than the at least one target DRAM device operates in a self-refresh mode in response to the selection signal based on the self-refresh signal, when the at least one target DRAM device operates in the normal mode.
A memory system comprising:
- a selection circuit comprising a plurality of selectors configured to select target dynamic random access memory (DRAM) devices from among a plurality of DRAM devices;
- a plurality of stabilization circuits configured to provide a self-refresh signal to the plurality of DRAM devices;
- and
- a DRAM controller configured to output a clock enable signal to the selection circuit and output a selection signal to select the target DRAM devices,
- wherein the plurality of selectors is configured to select the target DRAM devices in response to the selection signal,
- wherein the target DRAM devices are configured to operate in a normal mode in response to the clock enable signal, and
- wherein one or more stand-by DRAM devices other than the target DRAM devices are configured to operate in a self-refresh mode in response to the selection signal based on the self-refresh signal, when the target DRAM devices operate in the normal mode.
Dependencies are inferred from the claim text.