Self-timed reset pulse generator and memory device with self-timed reset pulse generator

A memory device, comprising:

• a memory cell unit, comprising:
• a plurality of bit lines, each bit line comprises a plurality of memory cells coupled in series;
• a Y-path circuit, for selecting one of the bit lines as intended;
• and
• a plurality of discharging and sensing units, respectively corresponding to bit lines for respectively discharging the bit lines and sensing data in the bit lines;
• and
• a self-timed reset pulse generator, comprising:
• a flip-flop circuit unit, receiving an input signal and a feedback signal and outputting a reset signal, wherein the reset signal is externally output for reset of discharging the bit lines of the memory cell unit;
• a tracking block, having a plurality of replicating cells coupled in series and replicating a structure of one of the bit lines in the memory cell unit, wherein the tracking block has a first terminal and a second terminal, wherein the first terminal and the second terminal are taking from the tracking block at a same location or two different locations;
• and
• a tracking circuit unit, receiving the reset signal and receiving the first terminal and the second terminal for respectively discharging the tracking block at the first terminal and sensing a voltage level at the second terminal as triggered by the reset signal,
• wherein the track-out signal serving as the feedback signal to the flip-flop circuit changes from a first logic state to a second logic state to cause a logic state of the reset signal being changed when the voltage level at the second terminal in comparison is less than or equal to a threshold as predetermined.