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US 9,792,966 B2Granted
Page buffer and semiconductor memory device including the same
AssigneeSK hynix Inc.
InventorYeonghun Lee
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device may include a memory cell array including a plurality of memory cells, and a plurality of page buffers respectively coupled to a plurality of bit lines of the memory cell array, the page buffers being supplied with internal voltages to precharge the plurality of bit lines or to sense an amount of current flowing through the plurality of bit lines, during a sensing operation, wherein each of the page buffers converts the internal voltages into supply voltages having constant potential levels.
Claims10
A semiconductor memory device, comprising:
- a memory cell array including a plurality of memory cells;
- and
- a plurality of page buffers respectively coupled to a plurality of bit lines of the memory cell array, the page buffers being supplied with internal voltages to precharge the plurality of bit lines or to sense an amount of current flowing through the plurality of bit lines, during a sensing operation,
- wherein each of the page buffers comprises a current determination circuit,
- the current determination circuit suitable for regulating a down converting voltage of the internal voltages to an internal down converting voltage having a constant potential level and performs an operation for sensing the amount of current by using an regulated internal down converting voltage during the sensing operation.
2 more elements
A page buffer, comprising:
- a bit line coupling unit coupled between a bit line to which a plurality of memory cells coupled and a control node, the bit line coupling unit being suitable for electrically coupling the bit line to the control node in response to a bit line coupling signal;
- a clamp circuit supplied with a first internal voltage to precharge the bit line and a sensing node, the clamp circuit being suitable for adjusting a potential level of the sensing node depending on an amount of current of the bit line;
- a current determination circuit suitable for generating a supply voltage by regulating a second internal voltage to a constant level and adjusting an amount of current output by using an regulated supply voltage in response to the sensing node potential level in the clamp circuit during a sensing operation;
- and
- a latch circuit suitable for storing data corresponding to the amount of current adjusted by the current determination circuit.
2 more elements
Dependencies are inferred from the claim text.