Sense amplifier for memory device
AssigneesSTMicroelectronics S.r.l., STMicroelectronics (Rousset) SAS
InventorsFrancesco La Rosa, Gineuve Alieri
Life of this patent
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Abstract
A read-amplifier circuit includes a core with a first input and a second input that are intended to receive in a measurement phase a differential signal arising from a first bit line and from a second bit line of the memory device. The circuit also includes a memory element with two inverters coupled in a crossed manner. The first and second inputs are respectively connected to two of the power supply nodes of the inverters via two transfer capacitors. A first controllable circuit is configured to temporarily render the memory element floating during an initial phase preceding the measurement phase and during the measurement phase.
Claims21
A method of operating a memory device comprising a read-amplifier circuit that comprises a core comprising first and second power supply terminals and a memory element with two crossed-coupled inverters, the method comprising:
- performing an initial phase by disconnecting power supply nodes of the memory element from the first and second power supply terminals so as to bring the memory element to an equilibrium state;
- and
- after performing the initial phase, performing a measurement phase to measure a differential signal present at two inputs of the core and arising from two bit lines of the memory device, the measurement phase comprising detecting a difference between slopes of signals present at the two inputs of the core and delivering the differential signal to two power supply nodes of the inverters via two transfer capacitors and breaking the equilibrium state while keeping the power supply nodes of the memory element disconnected from the first and second power supply terminals.
A read-amplifier circuit for a memory device, comprising:
- a core comprising a first input and a second input that are configured to receive in a measurement phase a differential signal arising from a first bit line and from a second bit line of the memory device;
- and
- a memory element with first and second inverters coupled in a crossed manner, wherein the first and second inputs are respectively connected to two of power supply nodes of the first and second inverters via first and second transfer capacitors, the memory element further comprising a first controllable circuit configured to temporarily render the memory element floating during an initial phase preceding the measurement phase and during the measurement phase.
A memory device, comprising:
- a first bit line;
- a second bit line;
- a first amplifier input coupled to the first bit line:
- a second amplifier input coupled to the second bit line;
- a first power supply node;
- a second power supply node;
- a first inverter comprising a first NMOS transistor and a first PMOS transistor coupled in series between the first power supply node and the second power supply node, wherein a source of the first NMOS transistor is coupled to the first power supply node and a source of the first PMOS transistor is coupled to the second power supply node, and wherein a drain of the first NMOS transistor is coupled to a drain of the first PMOS transistor;
- a second inverter comprising a second NMOS transistor and a second PMOS transistor coupled in series between the first power supply node and the second power supply node, wherein a source of the second NMOS transistor is coupled to the first power supply node and a source of the second PMOS transistor is coupled to the second power supply node, and wherein a drain of the second NMOS transistor is coupled to a drain of the second PMOS transistor;
- a first switch coupled between the first power supply node and the source of the first NMOS transistor;
- a second switch coupled between the second power supply node and the source of the first PMOS transistor;
- a third switch coupled between the first power supply node and the source of the second NMOS transistor;
- a fourth switch coupled between the second power supply node and the source of the second PMOS transistor;
- a first transfer capacitor coupled between the first amplifier input and the source of the first NMOS transistor;
- and
- a second transfer capacitors coupled between the second amplifier input and the source of the second NMOS transistor.
Dependencies are inferred from the claim text.