Signal driver circuit having adjustable output voltage for a high logic level output signal
AssigneeMicron Technology, Inc.
InventorSeong-Hoon Lee
Life of this patent
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Abstract
A signal driver circuit having an adjustable output voltage for a high-logic level output signal. The signal driver circuit includes a signal driver configured to output a first logic level signal having a first voltage and output a second logic level signal having a second voltage according to an input signal. A voltage controlled voltage supply coupled to the signal driver provides the first voltage for the first logic level signal. The magnitude of the first voltage provided by the voltage controlled voltage supply is based on a bias voltage. A bias voltage generator can be coupled to the voltage controlled voltage supply to provide the bias voltage.
Claims19
An apparatus comprising:
- a first transistor of a first channel type;
- a second transistor of the first channel type, the second transistor being coupled in series to the first transistor between a first voltage node and an output node;
- and
- a third transistor of the first channel type, the third transistor being coupled between the output node and a second voltage node,
- wherein the first transistor is configured to receive a bias voltage at a gate thereof and wherein the second transistor is provided at a gate with a first input signal and the third transistor is provided at a gate with a second input signal, the first and second input signals being complementary to each other.
An apparatus comprising:
- a first transistor of a first channel type, the first transistor including a gate configured to receive a bias voltage;
- a second transistor of the first channel type, the second transistor being coupled in series to the first transistor between a first voltage node and an output node;
- a third transistor of the first channel type, the third transistor being coupled between the output node and a second voltage node, wherein each of the first, second and third transistors is of an N channel type;
- and
- a bias voltage generator configured to provide the bias voltage, the bias voltage generator comprising:
- a fourth transistor coupled to the first transistor;
- a voltage supply circuit coupled between the fourth transistor and the second voltage node, and configured to provide a constant voltage;
- and
- a resistive load coupled between the first voltage node and the fourth transistor.
A memory comprising:
- an array of memory cells;
- a read circuit configured to access the array to produce first and second read data signals in relation to data stored in the array, the first and second read data signals being complementary to each other;
- and
- an output buffer comprising:
- first and second transistors coupled in series between a first voltage node and an output node, and
- a third transistor coupled between the output node and a second voltage node,
- wherein the first, second and third transistors are of the same channel type as each other;
- wherein the first transistor has a gate configured to be supplied with a constant voltage;
- wherein the second transistor has a gate configured to be supplied with the first read data signal;
- and
- wherein the third transistor has a gate configured to be supplied with the second read data signal.
An apparatus comprising:
- first and second voltage nodes;
- an output node;
- and
- an output driver coupled to the first and second voltage nodes and the output node, the output driver comprising:
- a first transistor of a first channel type coupled between the first voltage node and the output node and including agate configured to receive a bias voltage, the bias voltage being constant regardless of a voltage at the output node;
- a second transistor of the first channel type coupled in series to the first transistor between the first voltage node and the output node and including a gate configured to receive a first signal;
- and
- a third transistor of the first channel type coupled between the output node and the second voltage node and including a gate configured to receive a second signal, the second signal being complementary to the first signal.
Dependencies are inferred from the claim text.