Shift register unit, gate driving device and display device
AssigneesBoe Technology Group Co., Ltd., Beijing Boe Display Technology Co., Ltd.
InventorZheng Wang
Life of this patent
Estimating the term…
Abstract
The present disclosure provides a shift register unit including a pull-up module, an input module, a reset module, a first pull-down module, a second pull-down module, a first control module, a second control module, a first state clearing module, and a second state clearing module. The shift register unit utilizes a first clock signal and a second clock signal to cause the first and second pull-down modules to pull down alternately, in order to maintain the stability of the output signal. Furthermore, each of the TFTs in the circuit structure has a duty cycle smaller than 50%, so that the lifetime of TFTs is greatly increased. The present disclosure further provides a gate driving device and a display device using the shift register unit.
Claims13
A shift register unit comprising:
- a pull-up module;
- an input module;
- a reset module;
- a first pull-down module;
- a second pull-down module;
- a first control module;
- a second control module;
- a first state clearing module;
- and a second state clearing module;
- wherein
- the pull-up module is connected to a first clock signal port, a pull-up control node (PU) and a signal output end, and configured to pull up a signal outputted from the signal output end to high level according to a potential of the pull-up control node and a first clock signal inputted to the first clock signal port, said pull-up control node being a connection point between the pull-up module and the input module;
- the input module is connected to a signal input end and the pull-up control node, and configured to control the potential of the pull-up control node according to a signal inputted to the signal input end;
- the reset module is connected to a reset signal end, the first clock signal port, the pull-up control node and the signal output end, and configured to pull down the potential of the pull-up control node and the signal outputted from the signal output end to low level according to a signal inputted to the reset signal end and the first clock signal;
- the first pull-down module is connected to the first clock signal port, a second clock signal port to which a second clock signal is inputted, a first control node, the pull-up control node and the signal output end, and configured to pull down the potential of the pull-up control node and the signal outputted from the signal output end to low level when the potential of the first clock signal is high and the potential of the second clock signal is low, the first control node being a connection point between the first pull-down module and the first control module;
- the second pull-down module is connected to the first clock signal port, the second clock signal port, a second control node, the pull-up control node and the signal output end, and configured to pull down the potential of the pull-up control node and the signal outputted from the signal output end to low level when the potential of the first clock signal is low and the potential of the second clock signal is high, the second control node being a connection point between the second pull-down module and the second control module;
- the first control module is connected to the signal output end and the first control node, and configured to disable the first pull-down module when a signal is outputted from the signal output end;
- the second control module is connected to the signal input end and the second control node, and configured to disable the second pull-down module when a signal is inputted to the signal input end;
- the first state clearing module is connected to the second clock signal port and the first control node, and configured to clear the state of the first pull-down module when the potential of the second clock signal is high;
- and
- the second state clearing module is connected to the first clock signal port and the second control node, and configured to clear the state of the second pull-down module when the potential of the first clock signal is high.
Dependencies are inferred from the claim text.