Gate drive circuit, array substrate, display panel and display device

An array substrate, comprising:

• a display area;
• and
• a non-display area surrounding the display area, wherein N gate lines are arranged in the display area, and a gate drive circuit is arranged in the non-display area,
• wherein the gate drive circuit comprises:
• N shift register units, each of which is connected with one of N gate lines of a display panel respectively;
• and
• 2M clock signal lines configured to provide the N shift register units with clock signals, wherein each of the N shift register units is connected with exactly 2M/2 clock signal lines,
• wherein:
• N is an even number, and M is a natural number larger than or equal to 2,
• a trigger signal terminal of the first shift register unit is connected with a first initial trigger signal line, and a trigger signal terminal of the p-th shift register unit is connected with an output terminal of the (p−1)-th shift register unit, wherein p=2, 3, . . . , N,
• an end signal terminal of the r-th shift register unit is connected with an output terminal of the (r+2M-1)-th shift register unit, wherein r=1, 2, . . . , N−2M-1,
• a plurality of low level signal terminals of the shift register units are connected with a first low level signal line,
• a plurality of reset signal terminals of the shift register units are connected with a reset signal line,
• forward scan signal terminals of the shift register units are connected with a first scan signal line,
• backward scan signal terminals of the shift register units are connected with a second scan signal line, and
• the trigger signal terminal of the p-th shift register unit is connected with the output terminal of the (p−1)-th shift register unit through the (p−1)-th gate line.

A display panel, comprising an array substrate, wherein the array substrate comprises a display area and a non-display area surrounding the display area, wherein N gate lines are arranged in the display area, and a gate drive circuit is arranged in the non-display area,

• wherein the gate drive circuit comprises:
• N shift register units, each of which is connected with one of N gate lines of a display panel respectively;
• and
• 2M clock signal lines configured to provide the N shift register units with clock signals, wherein each of the N shift register units is connected with exactly 2M/2 clock signal lines, wherein:
• N is an even number, and M is a natural number larger than or equal to 2,
• a trigger signal terminal of the first shift register unit is connected with a first initial trigger signal line, and a trigger signal terminal of the p-th shift register unit is connected with an output terminal of the (p−1)-th shift register unit, wherein p=2, 3, . . . , N,
• an end signal terminal of the r-th shift register unit is connected with an output terminal of the (r+2M-1)-th shift register unit, wherein r=1, 2, . . . , N−2M-1,
• a plurality of low level signal terminals of the shift register units are connected with a first low level signal line,
• a plurality of reset signal terminals of the shift register units are connected with a reset signal line,
• forward scan signal terminals of the shift register units are connected with a first scan signal line,
• backward scan signal terminals of the shift register units are connected with a second scan signal line, and
• the trigger signal terminal of the p-th shift register unit is connected with the output terminal of the (p−1)-th shift register unit through the (p−1)-th gate line.

A display device, comprising a display panel, wherein the display panel comprises an array substrate, wherein the array substrate comprises a display area and a non-display area surrounding the display area, wherein there N gate lines are arranged in the display area, and a gate drive circuit is arranged in the non-display area,

• wherein the gate drive circuit comprises:
• N shift register units, each of which is connected with one of N gate lines of a display panel respectively;
• and
• 2M clock signal lines configured to provide the N shift register units with clock signals, wherein each of the N shift register units is connected with exactly 2M/2 clock signal lines, wherein:
• N is an even number, and M is a natural number larger than or equal to 2,
• a trigger signal terminal of the first shift register unit is connected with a first initial trigger signal line, and a trigger signal terminal of the p-th shift register unit is connected with an output terminal of the (p−1)-th shift register unit, wherein p=2, 3, . . . , N,
• an end signal terminal of the r-th shift register unit is connected with an output terminal of the (r+2M-1)-th shift register unit, wherein r=1, 2, . . . , N−2M-1,
• a plurality of low level signal terminals of the shift register units are connected with a first low level signal line,
• a plurality of reset signal terminals of the shift register units are connected with a reset signal line,
• forward scan signal terminals of the shift register units are connected with a first scan signal line,
• backward scan signal terminals of the shift register units are connected with a second scan signal line, and
• the trigger signal terminal of the p-th shift register unit is connected with the output terminal of the (p−1)-th shift register unit through the (p−1)-th gate line.