System and method for securing embedded controller communications by providing a security handshake
AssigneeDell Products L.P.
InventorsRichard M. Tonry, Matthew G. Page
Life of this patent
Estimating the term…
Abstract
An information handling system includes a processor operable to receive a system management interrupt, and an embedded controller coupled to the processor via a primary interface and via a system management interrupt interface. The embedded controller receives a command to enable address decoding from the processor via the primary interface, sends the system management interrupt via the system management interrupt interface in response to receiving the command, and receives an indication from the processor via the primary interface, the indication including a determination if the processor was operating in a system management mode when the processor sent the command.
Claims20
An information handling system, comprising:
- a processor including a primary interface and a system management interrupt interface, wherein the processor receives a system management interrupt via the system management interface;
- and
- an embedded controller coupled to the processor via the primary interface and via the system management interrupt interface, wherein the embedded controller:
- receives, via the primary interface, a command from the processor to enable address decoding;
- sends, via the system management interrupt interface, the system management interrupt to the processor in response to receiving the command;
- and
- receives, via the primary interface, an indication from the processor in response to sending the system management interrupt, wherein the indication indicates whether or not the processor was operating in a system management mode when the processor sent the command.
An information handling system, comprising:
- a processor including a primary interface and a system management interrupt interface, wherein the processor receives a system management interrupt via the system management interface;
- and
- an embedded controller coupled to the processor via the primary interface and via the system management interrupt interface, wherein the embedded controller:
- receives, via the primary interface, a management transaction from the processor;
- and
- in response to receiving the management transaction:
- sends, via the system management interrupt interface, a system management interrupt to the processor;
- and
- receives, via the primary interface, an indication from the processor in response to the system management interrupt, wherein the indication indicates whether or not the processor was operating in a system management mode when the processor sent the management transaction.
A non-transitory computer-readable medium including code for performing a method, the method comprising:
- receiving, at an embedded controller of an information handling system, from a processor of the information handling system, a command to configure address decoding, wherein the embedded controller is coupled to the processor via a primary interface and via a system management interrupt interface, and the command is received via the primary interface;
- and
- in response to receiving the management transaction:
- sending, via the system management interrupt interface, the system management interrupt to the processor in response to receiving the command;
- and
- receiving, via the primary interface, an indication from the processor in response to the system management interrupt, wherein the indication indicates whether or not the processor was operating in a system management mode when the processor sent the command.
Dependencies are inferred from the claim text.