Method and system for debugging a system on chip under test
AssigneeCadence Design Systems, Inc.
InventorsMeir Ovadia, Kalev Alpernas
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AssigneeCadence Design Systems, Inc.
InventorsMeir Ovadia, Kalev Alpernas
Estimating the term…
A method for debugging a system on chip (SoC) under test, the method may include executing a test code on the SoC, the test code designed to invoke a plurality of actions; recording output data from the SoC resulting from the executed test code; linking between actions detected in the recorded output data and actions of the plurality of actions of the test code by identifying a start and an end times of each of the detected actions in the recorded output data, and associating the identified start and end times with a start and an end times of actions of the plurality of actions of the test code; and causing display, via a graphical user interface, of a waveform representation of the detected actions over time, a representation of the test code and a representation of the output log.
A method for debugging a system on chip (SoC) under test, the method comprising:
A system for debugging a system on chip (SoC) under test, the system comprising:
A non-transitory computer readable storage medium for debugging a system on chip (SoC) under test, having stored thereon instructions that, when executed by a processor, will cause the processor to:
Dependencies are inferred from the claim text.