US 9,792,400 B2Granted

Determination of flip-flop count in physical design

AssigneeCavium, Inc.

InventorsChirinjeev Singh, Nikhil Jayakumar, Weihuang Wang, Weinan Ma, Daman Ahluwalia

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Abstract

System and method of determining flip-flop counts of interconnects of a physical layout during integrated circuit (IC) design. The outputs of each logic block are defined as primary inputs, and the inputs of each logic block are defined as primary outputs. Each interconnect is traversed from a primary input a primary output to identify the flip-flops and determine the flip-flop count. If an interconnect has a greater flip-flop count than an RTL estimated count, measures are taken to reduce the need for flip-flops with the current routing design. If the interconnect has a smaller flip-flop count than an RTL estimated count, additional flip-flops are inserted.

Claims19

Dependent claims

A computer implemented method of determining flip-flop counts of interconnects of a physical layout during integrated circuit (IC) design, said computer implemented method comprising:

accessing, by a processor, said physical layout comprising said interconnects disposed between a first logic block and a second logic block and flip-flops in said interconnects;
accessing, by the processor, identifications of start points and end points of said interconnects, wherein said start points correspond to outputs of said first logic block, and wherein said end points correspond to inputs of said second logic block;
assigning, by the processor, said start points as primary inputs;
assigning, by the processor, said end points as primary outputs;
traversing, by the processor, from said primary inputs to said primary outputs to identify said flip-flops in said interconnects;
determining, by the processor, respective numbers of flip-flops in said interconnects based on said traversing;
determining, by the processor, an estimated number of flip-flops for respective interconnects between said primary inputs and said primary outputs, wherein said estimated number is determined based on a Register-Transfer-Level (RTL) design of said physical layout;
comparing, by the processor, said respective numbers of flip-flops with said estimated number of flip-flops;
and
determining, by the processor, whether to insert additional flip-flops in said interconnects based on said comparison.

7 more elements

A system comprising:

a processor;
memory coupled to said processor and comprising instructions that, when executed by said processor, cause the system to perform a method of inserting flip-flops in interconnects in an interface between logic blocks during integrated circuit (IC) design, said method comprising:
inserting said flip-flops in said interconnects based on timing analysis report, a set of constraints, and timing requirements;
defining start points of said interconnects as primary inputs;
defining end points of said interconnects as primary outputs;
providing said primary inputs and said primary outputs to a program configured for logic equivalence check (LEC);
determining respective numbers of flip-flops in said interconnects based on a processing result generated by said program;
comparing said respective numbers of flip-flops with a count limit for flip-flop insertions, wherein said count limit is defined for respective interconnects of said interconnects in logic design based on estimated timing requirements;
and
determining whether to insert additional flip-flops in said interconnects based on said comparison.

7 more elements

Dependencies are inferred from the claim text.