Array of processor core circuits with reversible tiers

A method, comprising:

• routing packets between multiple tiers of core circuits via multiple switches;
• wherein each tier comprises at least one core circuit;
• wherein each core circuit comprises a pre-determined number of interconnect pads physically positioned such that the interconnect pads are symmetric across one or more mirroring dimensions;
• wherein interconnect pads of each core circuit align with interconnect pads of a different core circuit in response to one of face-to-back bonding, face-to-face bonding, or back-to-back bonding between the core circuit and the different core circuit;
• and
• wherein interconnect pads of each core circuit include a multiplexor structure configured to select between a first set of buses or a second set of buses for exchanging signals between the core circuit and a different core circuit, the first set of buses selected in response to face-to-back bonding between the core circuit and the different core circuit, and the second set of buses selected in response to one of face-to-face bonding or back-to-back bonding between the core circuit and the different core circuit.

A non-transitory computer program product comprising a computer-readable storage medium having program code embodied therewith, the program code being executable by a computer to:

• route packets between multiple tiers of core circuits via multiple switches;
• wherein each tier comprises at least one core circuit;
• wherein each core circuit comprises a pre-determined number of interconnect pads physically positioned such that the interconnect pads are symmetric across one or more mirroring dimensions;
• wherein interconnect pads of each core circuit align with interconnect pads of a different core circuit in response to one of face-to-back bonding, face-to-face bonding, or back-to-back bonding between the core circuit and the different core circuit;
• and
• wherein interconnect pads of each core circuit include a multiplexor structure configured to select between a first set of buses or a second set of buses for exchanging signals between the core circuit and a different core circuit, the first set of buses selected in response to face-to-back bonding between the core circuit and the different core circuit, and the second set of buses selected in response to one of face-to-face bonding or back-to-back bonding between the core circuit and the different core circuit.