US 9,792,247 B2Granted

Systems and methods for chip to chip communication

AssigneeQUALCOMM Incorporated

InventorsJason Alan Thurston, Kenneth Luis Arcudia

Life of this patent

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Abstract

Systems and methods for chip to chip communication are disclosed. In an exemplary aspect, a chip to chip link comprises a master device having a data transmitter, a clock, a clock transmitter, a phase locked loop (PLL) associated with the clock, and a receiver. The chip to chip link also comprises a slave device that has a data transmitter, a clock receiver, and a data receiver. Noticeably absent from the slave device is a clock or a PLL. By removing the clock from the slave device, the slave device does not have the power consuming element of a slave PLL. Further, because the slave device does not have a clock which would normally have to acquire a new frequency and settle, the master clock may change frequency relatively quickly and vary the frequency across many frequencies, not just one or two predefined frequencies.

Claims19

Dependent claims

A master integrated circuit (IC) comprising:

a bus interface configured to be coupled to an interchip bus;
a transmitter comprising a driver, the driver outputting a data signal to the bus interface for transmission across the interchip bus;
a receiver coupled to the bus interface;
a clock data recovery (CDR) circuit operatively coupled to the receiver;
a phase locked loop (PLL) receiving a reference clock signal and outputting a clock signal to the driver of the transmitter and the CDR circuit, wherein the transmitter outputs a master clock signal onto the interchip bus through the bus interface;
a control system operatively coupled to the PLL and the CDR circuit, the control system configured to change a frequency of the master clock signal by controlling the PLL, wherein data transmission continues during frequency change independent of clock activity at a remote slave IC;
and
a temperature control circuit operatively coupled to the control system and the CDR circuit, wherein the control system wakes the CDR circuit based on changes in temperature and the temperature control circuit.

5 more elements

A system comprising:

an interchip bus;
a first integrated circuit (IC) comprising:
a first bus interface configured to be coupled to the interchip bus;
a first transmitter comprising a first driver, the first driver outputting a first data signal to the first bus interface for transmission across the interchip bus;
a first receiver coupled to the first bus interface;
a first clock data recovery (CDR) circuit operatively coupled to the first receiver;
a first control system operatively coupled to the first CDR circuit;
and
a temperature control circuit operatively coupled to the first control system and the first CDR circuit, wherein the control system wakes the first CDR circuit based on changes in temperature and the temperature control circuit;
and
a second IC comprising:
a second bus interface configured to be coupled to the interchip bus;
a second transmitter comprising a second driver, the second driver outputting a second data signal to the second bus interface for transmission across the interchip bus;
a second receiver coupled to the second bus interface, the second receiver configured to extract a clock signal from a signal received from the first IC through the interchip bus;
a second CDR circuit operatively coupled to the second receiver;
and
a second control system operatively coupled to the second receiver and the second CDR circuit, the second control system configured to operate on the clock signal extracted by the second receiver without reference to an internal phase locked loop (PLL) or internal clock;
and
a sole active PLL shared between the first IC and the second IC, the sole active PLL configured to provide the clock signal for use by both the first IC and the second IC.

16 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/801,310Filed 16 Jul 2015 · us provisional application
Priority: 18 Jul 2014
Published: US 2016/0019183 A121 Jan 2016
Granted: 17 Oct 2017
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

G06F 13/4291
On a serial bus, e.g. I2C bus, SPI bus: using a clocked protocol
G06F 1/08
Generating or distributing clock signals or signals derived directly therefrom: clock generators with changeable or programmable clock frequency
G06F 13/364
With centralised access control: using independent requests or grants, e.g. using separated request and grant lines
Y02D 10/00
Energy efficient computing