Lower-power scrambling with improved signal integrity

A scrambler circuit, comprising:

• a linear feedback shift register (LFSR) to generate an X-bit scrambling code;
• a scrambling logic block to:
• select one or more bits of a previously generated scrambling code for modification, wherein the one or more bits correspond to one or more lanes over which scrambled data is to be transmitted, and
• modify the one or more bits of the previously generated scrambling code to values of corresponding bits of the X-bit scrambling code to generate a modified scrambling code, wherein the one or more lanes include fewer than all lanes over which data scrambled with the modified scrambling code is to be transmitted;
• and
• a signal combining circuit to apply the modified scrambling code to scramble a Z-bit transmit signal to output to a receiving device, where Z is equal to or greater than X.

A descrambler circuit, comprising:

• a linear feedback shift register (LFSR) to generate an X-bit scrambling code;
• a scrambling logic block to
• select one or more bits of a previously generated scrambling code for modification, wherein the one or more bits correspond to one or more lanes over which scrambled data is to be transmitted, and
• modify the one or more bits of the previously generated scrambling code to values of corresponding bits of the X-bit scrambling code to generate a modified scrambling code, wherein the one or more lanes include fewer than all lanes over which data scrambled with the modified scrambling code is to be transmitted;
• and
• a signal combining circuit to apply the modified scrambling code to unscramble a Z-bit received signal received from a transmitting device, where Z is equal to or greater than X.

An electronic device with a memory subsystem, comprising:

• a memory controller having a scrambler circuit including
• a linear feedback shift register (LFSR) to generate an X-bit scrambling code at the memory controller;
• a scrambling logic block to
• select one or more bits of a previously generated scrambling code for modification, wherein the one or more bits correspond to one or more lanes over which scrambled data is to be transmitted, and
• modify the one or more bits of the previously generated scrambling code to values of corresponding bits of the X-bit scrambling code to generate a modified scrambling code, wherein the one or more lanes include fewer than all lanes over which data scrambled with the modified scrambling code is to be transmitted;
• and
• a signal combining circuit to apply the modified scrambling code to scramble a Z-bit transmit signal to output to a memory device, where Z is equal to or greater than X;
• an input/output (I/O) interface coupled to the memory controller;
• and
• a memory device coupled to the memory controller over the I/O interface, the memory device having a scrambler circuit including
• a linear feedback shift register (LFSR) to generate the X-bit scrambling code at the memory device;
• a scrambling logic block to generate the modified scrambling code via the same operations as the scrambling logic block of the memory controller;
• a signal combining circuit to apply the modified scrambling code to unscramble the Z-bit transmit signal received from the memory controller;
• and
• a touchscreen display coupled to generate a display based on data accessed from the memory device.