Peripheral component interconnect express (PCIe) devices with efficient memory mapping by remapping a plurality of base address registers (BARs)

A method operable in a Peripheral Component Interconnect Express (PCIe) device communicatively coupled to a host system, the method comprising:

• configuring a computer memory with a plurality of Base Address Registers (BARs) when instructed by the host system;
• mapping addresses of a processor of the PCIe device to the BARs for routing PCIe packets from the host system;
• processing PCIe packets from the BARs through the addresses of the processor;
• determining that the host system is reconfiguring the BARs in the computer memory;
• and
• based on the determination:
• marking PCIe packets existing in the computer memory as old;
• changing the BARs in the computer memory by reallocating the computer memory as directed by the host system;
• marking PCIe packets received after the BARs reconfiguration as new;
• processing the old PCIe packets from the computer memory based on their addresses of the address space until a new PCIe packet is reached;
• and
• remapping the BARs to the addresses of the address space after the new PCIe packet is reached.

A non-transitory computer readable medium comprising instructions that, when executed by a processor on a Peripheral Component Interconnect Express (PCIe) device, direct the processor to:

• map addresses of a processor of the PCIe device to Base Address Registers (BARs) of a computer memory of the PCIe device for routing PCIe packets from the host system;
• process the PCIe packets from the BARs through the addresses of the processor;
• determine that the host system is reconfiguring the BARs in the computer memory;
• and
• based on the determination:
• mark PCIe packets existing in the computer memory as old;
• change the BARs in the computer memory by reallocating the computer memory as directed by the host system;
• mark PCIe packets received after the BARs reconfiguration as new;
• process the old PCIe packets from the computer memory based on their addresses of the address space until a new PCIe packet is reached;
• and
• remap the BARs to the addresses of the address space after the new PCIe packet is reached.

A Peripheral Component Interconnect Express (PCIe) device, comprising:

• a computer memory operable as a queue for packets from a host system;
• a packet transmit/receive core communicatively coupled to the computer memory and operable to direct the packets from the host system to the queue and to configure registers in the queue;
• and
• a local processor communicatively coupled to the computer memory and comprising an address space, wherein the local processor is operable to map registers of the queue to addresses of the address space to route packets from the computer memory,
• wherein the local processor is further operable to detect a change by the host system to the registers of the queue, to maintain mappings between the registers of the computer memory and the addresses of the address space, to flag packets received after the register change as new, to process packets received before the register change according to the maintained mappings, to change the mappings between the registers of the computer memory and the addresses of the address space when no other packets received before the register change remain, and to process the new packets according to the change between the registers of the computer memory and the addresses of the address space.

A method operable with a Peripheral Component Interconnect Express (PCIe) device, comprising:

• configuring registers in a queue of the PCIe device;
• queuing packets from a host system;
• mapping the registers of the queue to addresses of the address space to route packets from computer memory,
• detecting a change by the host system to the registers of the queue;
• maintaining mappings between the registers of the computer memory and the addresses of the address space;
• flagging packets received after the register change as new;
• processing packets received before the register change according to the maintained mappings;
• changing the mappings between the registers of the computer memory and the addresses of the address space when no other packets received before the register change remain;
• and
• processing the new packets according to the change between the registers of the computer memory and the addresses of the address space.