Techniques for escalating interrupts in a data processing system to a higher software stack level

A processing unit for a multithreaded data processing system, the processing unit comprising:

• an interrupt source controller (ISC);
• and
• an interrupt presentation controller (IPC) coupled to the ISC, wherein the IPC is configured to:
• receive a first event notification message (ENM) from the ISC, wherein the first ENM specifies a level, an event target number, a number of bits to ignore, and an event priority;
• determine a group of virtual processor threads that may be potentially interrupted based on the event target number, the number of bits to ignore, the level, and a process identifier (ID) when the level specified in the first ENM corresponds to a user level, wherein the event target number in the first ENM identifies a specific virtual processor thread, the number of bits to ignore in the first ENM identifies the number of lower-order bits to ignore with respect to the specific virtual processor thread when determining the group of virtual processor threads that may be potentially interrupted, and the level in the first ENM specifies a first software stack level;
• in response to at least one virtual processor thread within the group of virtual processor threads being dispatched and operating on an associated physical processor, determine whether the event priority in the first ENM is greater than an operating priority of the at least one virtual processor thread;
• and
• in response to the event priority in the first ENM not being greater than an operating priority of the at least one virtual processor thread, issue a first escalate message that includes a first escalate event number that is sourced from an interrupt context table (ICT) of the IPC, wherein the first escalate event number is used by the ISC to generate a second ENM that targets a second software stack level that is different than the first software stack level.

A data processing system, comprising:

• a memory;
• and
• a processing unit coupled to the memory, wherein the processing unit includes an interrupt source controller (ISC) and an interrupt presentation controller (IPC) coupled to the ISC, and wherein the IPC is configured to:
• receive a first event notification message (ENM) from the ISC, wherein the first ENM specifies a level, an event target number, a number of bits to ignore, and an event priority;
• determine a group of virtual processor threads that may be potentially interrupted based on the event target number, the number of bits to ignore, the level, and a process identifier (ID) when the level specified in the first ENM corresponds to a user level, wherein the event target number in the first ENM identifies a specific virtual processor thread, the number of bits to ignore in the first ENM identifies the number of lower-order bits to ignore with respect to the specific virtual processor thread when determining the group of virtual processor threads that may be potentially interrupted, and the level in the first ENM specifies a first software stack level;
• in response to at least one virtual processor thread within the group of virtual processor threads being dispatched and operating on an associated physical processor, determine whether the event priority in the first ENM is greater than an operating priority of the at least one virtual processor thread;
• and
• in response to the event priority in the first ENM not being greater than an operating priority of the at least one virtual processor thread, issue a first escalate message that includes a first escalate event number that is sourced from an interrupt context table (ICT) of the IPC, wherein the first escalate event number is used by the ISC to generate a second ENM that targets a second software stack level that is different than the first software stack level.