Techniques for queueing interrupts in a data processing system
AssigneeInternational Business Machines Corporation
InventorsRichard L. Arndt, Florian A. Auernhammer
Life of this patent
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Abstract
A method of handling interrupts in a data processing system includes maintaining a first interrupt destination buffer (IDB) for a first interrupt handler routine (IHR) and a second IDB for a second IHR. Whether a received interrupt is associated with the first IHR or the second IHR is determined. In response to the received interrupt being associated with the first IHR, event information associated with the received interrupt is stored in the first IDB. In response to the received interrupt being associated with the second IHR, the event information associated with the received interrupt in stored in the second IDB.
Claims17
A method of handling interrupts in a data processing system, the method comprising:
- maintaining, by an interrupt routing controller (IRC), a first interrupt destination buffer (IDB) for a first interrupt handler routine (IHR) and a second IDB for a second IHR;
- receiving, by the IRC, an interrupt;
- determining, by the IRC, whether the received interrupt is associated with the first IHR or the second IHR;
- in response to the received interrupt being associated with the first IHR, storing, by the IRC, event information associated with the received interrupt in the first IDB;
- and
- in response to the received interrupt being associated with the second IHR, storing, by the IRC, the event information associated with the received interrupt in the second IDB, wherein the event information includes an event source number and a generation value that specifies whether a circular buffer associated with a respective one of the first and second IDBs has been completely traversed.
A processing unit for a multithreaded data processing system, the processing unit comprising:
- an interrupt source controller (ISC);
- an interrupt presentation controller (IPC);
- and
- an interrupt routing controller (IRC) coupled to the ISC and the IPC, wherein the IRC is configured to:
- maintain a first interrupt destination buffer (IDB) for a first interrupt handler routine (IHR) and a second IDB for a second IHR;
- receive an interrupt;
- determine whether the received interrupt is associated with the first IHR or the second IHR;
- in response to the received interrupt being associated with the first IHR, store event information associated with the received interrupt in the first IDB;
- and
- in response to the received interrupt being associated with the second IHR, store the event information associated with the received interrupt in the second IDB, wherein the event information includes an event source number and a generation value that specifies whether a circular buffer associated with a respective one of the first and second IDBs has been completely traversed.
A data processing system, comprising:
- a memory;
- and
- a processing unit coupled to the memory, wherein the processing unit is configured to:
- maintain a first interrupt destination buffer (IDB) for a first interrupt handler routine (IHR) and a second IDB for a second IHR;
- receive an interrupt;
- determine whether the received interrupt is associated with the first IHR or the second IHR;
- in response to the received interrupt being associated with the first IHR, store event information associated with the received interrupt in the first IDB;
- and
- in response to the received interrupt being associated with the second IHR, store the event information associated with the received interrupt in the second IDB, wherein the event information includes an event source number and a generation value that specifies whether a circular buffer associated with a respective one of the first and second IDBs has been completely traversed.
Dependencies are inferred from the claim text.