Back to results
US 9,792,230 B2Granted
Data input circuit of semiconductor apparatus
AssigneeSK hynix Inc.
InventorsJoon Woo Choi, Chang Ki Baek
Life of this patent
Estimating the term…
Abstract
A data input circuit of a semiconductor apparatus may include a plurality of parallelizing units corresponding to a plurality of input/output pads in a one-to-one manner, and a data control block configured to transmit serial test data, which may be input through less than all of the plurality of input/output pads, to the plurality of parallelizing units in response to first and second control signals.
Claims18
A data input circuit of a semiconductor apparatus, comprising:
- a plurality of parallelizing units corresponding to a plurality of input/output pads in a one-to-one manner;
- and
- a data control block comprising a plurality of first data processing units and a plurality of second data processing units,
- wherein, during a test mode, the plurality of first data processing units are configured to transmit a serial test data, which is input through less than all of the plurality of input/output pads, to less than all of the plurality of parallelizing units and all of the plurality of second data processing units in response to a first control signal and a second control signal,
- wherein, during the test mode, the plurality of second data processing units are configured to transmit the serial test data to remaining parallelizing units in response to the first control signal,
- and wherein, during a normal mode, the plurality of first data processing units and the plurality of second data processing units are configured to transmit a normal data, which is input through all of the plurality of input/output pads each by each, to all of the plurality of parallelizing units each by each in response to the first control signal.
3 more elements
A data input circuit of a semiconductor apparatus, comprising:
- a plurality of parallelizing units corresponding to a plurality of input/output pads in a one-to-one manner;
- a pattern conversion unit configured to convert a pattern of a serial test data, which is input through one of the plurality of input/output pads, and to generate plural test data having patterns different from each other;
- and
- a data control block comprising a plurality of first data processing units and a plurality of second data processing units,
- wherein, during a test mode, the plurality of first data processing units are configured to transmit the plural test data to less than all of the plurality of parallelizing units and all of the plurality of second data processing units in response to a first control signal and a second control signal,
- wherein, during the test mode, the plurality of second data processing units are configured to transmit the plural test data to remaining parallelizing units in response to the first control signal,
- and wherein, during a normal mode, the plurality of second data processing units are configured to transmit a normal data, which is input through remaining input/output pads, to the remaining parallelizing units in response to the first control signal.
4 more elements
Dependencies are inferred from the claim text.