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US 9,792,225 B2Granted
Host and computer system having the same
AssigneeSamsung Electronics Co., Ltd.
InventorsSeok-Min Kim, Kwan-Ho Kim, Mi-Kyung Kim
Life of this patent
Estimating the term…
Abstract
A host includes a cache including a plurality of cache lines, a command descriptor list configured to store a command transmitted from one of the plurality of cache lines, a host controller including a direct memory access (DMA) device that accesses the command descriptor list, and a processor configured to determine a size of the command descriptor list based on a size of the one of the plurality of cache lines.
Claims20
A host, comprising:
- a cache comprising a plurality of cache lines;
- a command descriptor list configured to store a command transmitted from one of the plurality of cache lines;
- a host controller comprising a direct memory access (DMA) device configured to access the command descriptor list;
- and
- a processor configured to determine a size of the command descriptor list based on a size of the one of the plurality of cache lines.
2 more elements
A computer system, comprising:
- a device;
- and
- a host configured to access the device,
- wherein the host comprises:
- a cache comprising a plurality of cache lines;
- a command descriptor list configured to store a command transmitted from one of the plurality of cache lines;
- a host controller comprising a direct memory access (DMA) device configured to access the command descriptor list;
- and
- a processor configured to determine a size of the command descriptor list based on a size of the one of the plurality of cache lines.
6 more elements
A host, comprising:
- a cache comprising a plurality of cache lines;
- a command descriptor list configured to store commands transmitted from the plurality of cache lines,
- wherein the command descriptor list comprises a plurality of command descriptors and each of the plurality of command descriptors comprises an empty space;
- a host controller comprising a direct memory access (DMA) device configured to access the command descriptor list;
- and
- a processor configured to determine a size of the empty spaces based on a size of each of the plurality of cache lines.
3 more elements
Dependencies are inferred from the claim text.