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US 9,792,224 B2Granted
Reducing latency by persisting data relationships in relation to corresponding data in persistent memory
AssigneeIntel Corporation
InventorsKarthik Kumar, Martin P. Dimitrov, Thomas Willhalm
Life of this patent
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Abstract
A processor or system may include a memory controller to store, in a pre-allocated portion of bit-addressable, random access persistent memory (PM), a relationship between a group of addresses being stored in the PM according to a set of instructions when executed. The memory controller is further to retrieve the relationship when accessing an address from the groups of addresses.
Claims25
An apparatus comprising:
- a memory controller to:
- store, in a pre-allocated portion of a bit-addressable, random access persistent memory, information indicating a relationship between a group of addresses being stored in the persistent memory according to a set of instructions, when executed;
- and
- retrieve the relationship from the information when accessing an address from the group of addresses.
1 more element
A processor comprising:
- a cache;
- a memory unit including a memory controller to store, in a pre-allocated portion of a bit-addressable, random access persistent memory disposed on a dual in-line memory module (DIMM), information indicating a relationship between a first address and an identified second address to which the first address links according to a set of instructions;
- wherein the memory controller is further to:
- retrieve the relationship from the information when accessing the first address;
- and
- prefetch data corresponding to the identified second address when reading the first address, to store the data locally in the cache.
3 more elements
A method comprising:
- storing, by a memory controller and in a pre-allocated portion of a bit-addressable, random access persistent memory, information indicating a relationship between a group of addresses being stored in the persistent memory according to a set of instructions, when executed;
- and
- retrieving, by the memory controller, the relationship from the information when accessing an address from the group of addresses.
A system comprising:
- a motherboard substrate having a first socket and a second socket, wherein a processor is inserted into the first socket and an integrated circuit containing bit-addressable, random access persistent memory is inserted into the second socket;
- wherein the processor comprises a memory controller to:
- store, in a pre-allocated portion of the persistent memory, information indicating a relationship between a group of addresses being stored in the persistent memory according to a set of instructions, when executed;
- and
- retrieve the relationship from the information when accessing an address from the group of addresses.
2 more elements
Dependencies are inferred from the claim text.