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AssigneeVia Alliance Semiconductor Co., Ltd.
InventorsBrent Bean, Colin Eddy
Estimating the term…
A system and method for determining memory ownership on a cache line basis for detecting self-modifying code with instructions that overlap cache line boundaries. An ownership index and a cache line address are entered into the ownership queue for each cache line. The cache lines are translated into instructions, and a straddle bit is set for each instruction that was derived from cache line data that overlapped two cache lines. A stale bit is set for any entry of the ownership queue that collides with a store instruction. Each instruction issued for execution is marked with a first exception when the stale bit of the corresponding ownership queue entry is set, or when the straddle bit of the issued instruction and a stale bit of a next sequential entry are both set. A first exception is performed for each instruction ready to retire that is marked with the first exception.
A processor that determines memory ownership on a cache line basis for detecting self-modifying code including code with instruction that overlaps cache line boundaries, said processor comprising:
A method of determining memory ownership on a cache line basis for detecting self-modifying code including code with instruction that overlaps cache line boundaries, comprising:
Dependencies are inferred from the claim text.