Command-driven translation pre-fetch for memory management units
AssigneeQUALCOMM Incorporated
InventorsJason Edward Podaima, Bohuslav Rychlik, Paul Christopher John Wiercienski, Kyle John Ernewein, Carlos Javier Moreira, Meghal Varia, Serag Gadelrab
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Abstract
Methods and systems for pre-fetching address translations in a memory management unit (MMU) of a device are disclosed. In an embodiment, the MMU receives a pre-fetch command from an upstream component of the device, the pre-fetch command including an address of an instruction, pre-fetches a translation of the instruction from a translation table in a memory of the device, and stores the translation of the instruction in a translation cache associated with the MMU.
Claims30
A method of pre-fetching address translations in a memory management unit (MMU) of a device, comprising:
- receiving, by the MMU, a pre-fetch command from an upstream component of the device, the pre-fetch command including an address of an instruction, the pre-fetch command received by the MMU before a request for the address of the instruction is received from the upstream component;
- pre-fetching, by the MMU, a translation of the address of the instruction from a translation table in a memory of the device before the MMU receives the request for the address of the instruction from the upstream component;
- storing, by the MMU, the translation of the address of the instruction in a translation cache associated with the MMU before the MMU receives the request for the address of the instruction from the upstream component;
- and
- receiving, by the MMU, the request for the address of the instruction from the upstream component.
An apparatus for pre-fetching address translations in a memory management unit (MMU) of a device, comprising:
- a logic circuit of the MMU configured to receive a pre-fetch command from an upstream component of the device, the pre-fetch command including an address of an instruction, the pre-fetch command received by the MMU before a request for the address of the instruction is received from the upstream component;
- a logic circuit of the MMU configured to pre-fetch a translation of the address of the instruction from a translation table in a memory of the device before the MMU receives the request for the address of the instruction from the upstream component;
- a logic circuit of the MMU configured to store the translation of the address of the instruction in a translation cache associated with the MMU before the MMU receives the request for the address of the instruction from the upstream component;
- and
- a logic circuit of the MMU configured to receive the request for the address of the instruction from the upstream component.
An apparatus for pre-fetching address translations in a memory management unit (MMU) of a device, comprising:
- means for receiving, by the MMU, a pre-fetch command from an upstream component of the device, the pre-fetch command including an address of an instruction, the pre-fetch command received by the MMU before a request for the address of the instruction is received from the upstream component;
- means for pre-fetching, by the MMU, a translation of the address of the instruction from a translation table in a memory of the device before the MMU receives the request for the address of the instruction from the upstream component;
- means for storing, by the MMU, the translation of the address of the instruction in a translation cache associated with the MMU before the MMU receives the request for the address of the instruction from the upstream component;
- and
- means for receiving, by the MMU, the request for the address of the instruction from the upstream component.
A non-transitory computer-readable medium for pre-fetching address translations in a memory management unit (MMU) of a device, comprising:
- at least one instruction instructing the MMU to receive a pre-fetch command from an upstream component of the device, the pre-fetch command including an address of an instruction, the pre-fetch command received by the MMU before a request for the address of the instruction is received from the upstream component;
- at least one instruction instructing the MMU to pre-fetch a translation of the address of the instruction from a translation table in a memory of the device before the MMU receives the request for the address of the instruction from the upstream component;
- at least one instruction instructing the MMU to store the translation of the address of the instruction in a translation cache associated with the MMU before the MMU receives the request for the address of the instruction from the upstream component;
- and
- at least one instruction instructing the MMU to receive the request for the address of the instruction from the upstream component.
Dependencies are inferred from the claim text.