US 9,792,213 B2 · Mitigating busy time in a high performance cache

Abstract

Various embodiments mitigate busy time in a hierarchical store-through memory cache structure including a cache directory associated with a memory cache. The cache directory is divided into a plurality of portions each associated with a portion of memory cache. A determination is made that a first subpipe of a shared cache pipeline comprises a non-store request. The shared pipeline is communicatively coupled to the plurality of portions of the cache directory. A store command is prevented from being placed in a second subpipe of the shared cache pipeline based on determining that a first subpipe of the shared cache pipeline comprises a non-store request. Simultaneous cache lookup operations are supported between the plurality of portions of the cache directory and cache write operations. Two or more store commands simultaneously processed in a shared cache pipeline communicatively coupled to the plurality of portions of the cache directory.

Claims18

Dependent claims

A method for mitigating busy time in a hierarchical store-through memory cache structure comprising a cache directory associated with a memory cache, where the cache directory is divided into a plurality of portions each associated with a portion of memory cache, the method comprising:

determining that a first subpipe of a shared cache pipeline comprises a non-store request, wherein the shared pipeline is communicatively coupled to the plurality of portions of the cache directory;
preventing, based on determining that a first subpipe of the shared cache pipeline comprises a non-store request, a store command from being placed in a second subpipe of the shared cache pipeline;
supporting simultaneous cache lookup operations between the plurality of portions of the cache directory and cache write operations;
and
processing, based on the supporting, two or more store commands simultaneously in a shared cache pipeline communicatively coupled to the plurality of portions of the cache directory.

2 more elements

An information processing device for mitigating busy time in a hierarchical store-through memory cache structure, the information processing device comprising:

a plurality of processing cores;
at least one memory cache communicatively coupled to the plurality of processing cores;
at least one cache directory associated with the at least one memory cache, wherein the at least one cache directory comprises a plurality of portions each associated with a portion of the at least one memory cache;
a shared cache pipeline communicatively coupled to the plurality of portions of the cache directory, wherein the shared cache pipeline comprises at least one pipeline partitioned into a first subpipe and at least a second subpipe;
and
at least one cache controller communicatively coupled to the at least one memory cache and the plurality of processing cores, wherein the at least one cache controller is configured to perform a method comprising:
determining that the first subpipe of a shared cache pipeline comprises a non-store request;
preventing, based on determining that a first subpipe of the shared cache pipeline comprises a non-store request, a store command from being placed in the second subpipe of the shared cache pipeline;
supporting simultaneous cache lookup operations between the plurality of portions of the cache directory and cache write operations;
and
processing, based on the supporting, two or more store commands simultaneously in a shared cache pipeline communicatively coupled to the plurality of portions of the cache directory.

8 more elements

Dependencies are inferred from the claim text.

Mitigating busy time in a high performance cache

Life of this patent

Mitigating busy time in a high performance cache

Life of this patent

Abstract

Claims18