Virtual shared cache mechanism in a processing device
AssigneeIntel Corporation
InventorsYen-Cheng Liu, Aamer Jaleel, Bongjin Jung, Zeshan A. Chishti, Adrian C. Moga, Eric Delano, Ren Wang
Life of this patent
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Abstract
In accordance with embodiments disclosed herein, there is provided systems and methods for providing a virtual shared cache mechanism. A processing device includes a plurality of clusters allocated into a virtual private shared cache. Each of the clusters includes a plurality of cores and a plurality of cache slices co-located within the plurality of cores. The processing device also includes a virtual shared cache including the plurality of clusters such that the cache data in the plurality of cache slices is shared among the plurality of clusters.
Claims20
A processing device, comprising:
- a plurality of sub-non-uniform memory access (sub-NUMA) clusters each comprising a plurality of cores, wherein each core of the plurality of cores comprising a plurality of cache slices co-located within the core;
- and
- a virtual shared cache comprising the plurality of sub-NUMA clusters, wherein cache capacity of the plurality of cache slices is shared among the plurality of sub-NUMA clusters.
A system comprising:
- a memory;
- and
- a processing device communicably coupled to the memory, wherein the processing device comprises:
- a plurality of sub-non-uniform memory access (sub-NUMA) clusters each comprising a plurality of cores, wherein each core of the plurality of cores comprising a plurality of cache slices co-located within the core;
- and
- a virtual shared cache comprising the plurality of sub-NUMA clusters, wherein cache capacity of the plurality of cache slices is shared among the plurality of sub-NUMA clusters.
A method comprising:
- allocating a plurality of sub-non-uniform memory access (sub-NUMA) clusters into a virtual shared cache, wherein each of the sub-NUMA clusters comprise a plurality of cores, each core of the plurality of cores comprising a plurality of cache slices co-located within the core;
- and
- sharing a cache capacity of the plurality of cache slices among the plurality of sub-NUMA clusters of the virtual shared cache.
A non-transitory machine-readable storage medium including data that, when accessed by a processing device, cause the processing device to perform operations comprising:
- allocating a plurality of sub-non-uniform memory access (sub-NUMA) clusters into a virtual shared cache, wherein each of the sub-NUMA clusters comprise a plurality of cores, each core of the plurality of cores comprising a plurality of cache slices co-located within the core;
- and
- sharing a cache capacity of the plurality of cache slices among the plurality of sub-NUMA clusters of the virtual shared cache.
Dependencies are inferred from the claim text.