US 9,792,211 B2Granted

Providing coherent merging of committed store queue entries in unordered store queues of block-based computer processors

AssigneeQUALCOMM Incorporated

InventorGregory Michael Wright

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Abstract

Providing coherent merging of committed store queue entries in unordered store queues of block-based computer processors is disclosed. In one aspect, a block-based computer processor provides a merging logic circuit communicatively coupled to an unordered store queue and cache memory. The merging logic circuit is configured to select a first store queue entry in the unordered store queue, and read its memory address, an age indicator, and a data value. The age indicator and the data value are stored in merged data bytes within a merged data buffer. The merging logic circuit then locates a remaining store queue entry having a memory address identical to the first selected store queue entry, and reads its age indicator and data value. Based on the age indicator and one or more age indicators of the merged data bytes within the merged data buffer, the data value is merged into the merged data buffer.

Claims24

Dependent claims

A block-based computer processor, comprising:

a cache memory;
an unordered store queue comprising a plurality of store queue entries;
and
a merging logic circuit communicatively coupled to and separate from the unordered store queue and the cache memory, comprising a merged data buffer for storing a plurality of merged data bytes;
the merging logic circuit configured to:
select a first committed store queue entry of the plurality of store queue entries of the unordered store queue;
read a memory address, a first age indicator, and a first data value from the first committed store queue entry;
store the first age indicator and the first data value in one or more merged data bytes of the plurality of merged data bytes of the merged data buffer;
for each remaining committed store queue entry of the plurality of store queue entries of the unordered store queue having an identical memory address as the first committed store queue entry:
read a second age indicator and a second data value from the remaining committed store queue entry;
and
merge the second data value into the one or more merged data bytes of the plurality of merged data bytes of the merged data buffer, based on a comparison of the second age indicator and one or more age indicators of the one or more merged data bytes;
and
output the plurality of merged data bytes of the merged data buffer to the cache memory.

11 more elements

A block-based computer processor, comprising:

a means for selecting a first committed store queue entry of a plurality of store queue entries of an unordered store queue;
a means for reading a memory address, a first age indicator, and a first data value from the first committed store queue entry;
a means for storing the first age indicator and the first data value in one or more merged data bytes of a plurality of merged data bytes of a merged data buffer;
for each remaining committed store queue entry of the plurality of store queue entries of the unordered store queue having an identical memory address as the first committed store queue entry:
a means for reading a second age indicator and a second data value from the remaining committed store queue entry;
and
a means for merging the second data value into the one or more merged data bytes of the plurality of merged data bytes of the merged data buffer, based on a comparison of the second age indicator and one or more age indicators of the one or more merged data bytes;
and
a means for outputting the plurality of merged data bytes of the merged data buffer to a cache memory.

6 more elements

A method for coherently merging committed store queue entries in an unordered store queue of a block-based computer processor, comprising:

selecting a first committed store queue entry of a plurality of store queue entries of the unordered store queue;
reading a memory address, a first age indicator, and a first data value from the first committed store queue entry;
storing the first age indicator and the first data value in one or more merged data bytes of a plurality of merged data bytes of a merged data buffer;
for each remaining committed store queue entry of the plurality of store queue entries of the unordered store queue having an identical memory address as the first committed store queue entry:
reading a second age indicator and a second data value from the remaining committed store queue entry;
and
merging the second data value into the one or more merged data bytes of the plurality of merged data bytes of the merged data buffer, based on a comparison of the second age indicator and one or more age indicators of the one or more merged data bytes;
and
outputting the plurality of merged data bytes of the merged data buffer to a cache memory.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/863,577Filed 24 Sep 2015
Published: US 2017/0091102 A130 Mar 2017
Granted: 17 Oct 2017
Term ends: Not estimatedThe source records don’t support an estimate.

Classification9 codes

G06F 12/0833
Using a bus scheme, e.g. with bus monitoring or watching means: in combination with broadcast means
G06F 9/3834
Operand accessing: maintaining memory consistency
G06F 9/3855
G06F 12/0855
Multiple simultaneous or quasi-simultaneous cache accessing: overlapped cache accessing, e.g. pipeline