Data recovery circuit, semiconductor storage device, and data recovery method
AssigneeKabushiki Kaisha Toshiba
InventorsYosuke Kondo, Kenji Yoshida
Life of this patent
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Abstract
According to one embodiment, a data recovery circuit includes an XOR operation unit, an erroneous bit position inferring unit, an error factor inferring unit, and an error provisionally determining unit. The XOR operation unit performs a bitwise XOR operation on M data sequences of N bits, where M and N are integers of two or greater. The erroneous bit position inferring unit infers an erroneous bit position based on the XOR operation result. The error factor inferring unit infers the inverted direction of the erroneous bit. The error provisionally determining unit performs bit inversion in the erroneous bit position, the direction of the bit inversion being opposite to the inferred inverted direction.
Claims17
A data recovery circuit comprising:
- an XOR operation unit that performs a bitwise XOR operation on M data sequences of N bits, where M and N are integers of two or greater;
- an erroneous bit position inferring unit that infers an erroneous bit position based on the XOR operation result;
- an error factor inferring unit that infers the inverted direction of the erroneous bit;
- and
- an error provisionally determining unit that performs bit inversion in the erroneous bit position, the direction of the bit inversion being opposite to the inferred inverted direction.
A semiconductor storage device comprising:
- a NAND memory that stores data;
- and
- a controller that controls the NAND memory,
- wherein the controller comprises:
- a data recovery circuit that infers an erroneous bit position based on a result of a bitwise XOR operation of M data sequences of N bits, where M and N are integers of two or greater, and that performs bit inversion in the erroneous bit position, the direction of the bit inversion being opposite to an inverted direction inferred for the erroneous bit;
- and
- an interface circuit that transmits/receives data to/from the NAND memory.
Dependencies are inferred from the claim text.