Method and apparatus for encoding and decoding data in memory system

A memory system comprising:

• a memory controller;
• and
• a memory device, the memory device including a memory cell array,
• the memory cell array including least a first memory page having a plurality of memory cells,
• the memory controller being configured to,
• receive a plurality of bits from an external device,
• generate a plurality of first data code words by performing error correcting code (ECC) encoding on the received plurality bits, each of the plurality of first data code words including first data bits and first redundancy bits, the first redundancy bits providing an initial error correction capability with respect to the first data bits,
• store the plurality of first data code words, respectively, as a plurality of data frames in the first memory page, and
• generate delta syndrome data, the generated delta syndrome data including at least a plurality of first stage delta syndromes corresponding to the plurality of first data code words, respectively, such that,
• for each first data code word, of the plurality of first data code words, the first stage delta syndrome that corresponds to the first data code word provides a first stage error correction capability, the first stage error correction capability being an additional error correction capability with respect to the initial error correction capability provided by the first redundancy bits of the first data code word.

A memory system comprising:

• a memory controller;
• and
• a memory device,
• the memory device including a memory cell array, the memory cell array including least a first memory page having a plurality of memory cells storing a plurality of stored bits;
• the memory controller is configured to perform a first hard read operation on the first memory page to generate a plurality of first data code words corresponding to the plurality of stored bits, the plurality of first data code words each including first data bits and first redundancy bits, the first redundancy bits providing an initial error correction capability,
• the memory controller is configured to perform a first error correcting code (ECC) decoding operation to correct errors among the first data code words using the initial error correction capabilities of the first redundancy bits of the first data code words,
• the memory controller is configured to determine whether or not to augment initial correction capabilities of one or more error code words,
• each of the one or more error code words being a first data code word, from among the plurality of first data code words, having a number of bits errors that exceeds an initial correction capability of the first redundancy bits of the first data code word, and
• the memory controller is configured such that, if the memory controller determines to augment the initial correction capabilities of one or more error code words,
• the memory controller generates one or more first delta syndromes corresponding, respectively, to the one or more error code words, each of the one or more first delta syndromes having a first additional error correction capability, and
• the memory controller augments the initial correction capabilities of the one or more error code words by performing a second error correcting code (ECC) decoding operation to correct errors among the one or more error code words using the initial error correction capabilities of the first redundancy bits of the one or more error code words augmented by the first additional error correction capabilities of the one or more first delta syndromes.