Transactional storage accesses supporting differing priority levels

A design structure tangibly embodied in a non-transitory machine-readable storage device for designing, manufacturing, or testing an integrated circuit, the design structure comprising:

• a processing unit, including:
• a processor core that, responsive to execution of a transactional memory instruction within the requesting memory transaction, said transactional memory instruction including a field that indicates a priority of the requesting memory transaction, outputs an indication of the priority of the requesting memory transaction;
• a cache memory, coupled to the processor core, that receives the indication of the priority of the requesting memory transaction and a transactional memory access request generated by execution of a transactional memory access instruction within the requesting memory transaction, wherein the transactional memory access request includes a target address of data to be accessed;
• transactional memory circuit configured to:
• responsive to the transactional memory access request, detect a conflict for the target address between the transactional memory access request and a transaction footprint of an existing memory transaction;
• access a priority of the existing memory transaction;
• and
• responsive to detecting the conflict, resolve the conflict by causing the cache memory to fail one of the requesting memory transaction and the existing memory transaction based at least in part on the relative priorities of the requesting memory transaction and the existing memory transaction, wherein the transactional memory logic is configured to resolve the conflict by:
• causing the cache memory to fail the existing memory transaction when the requesting memory transaction has a higher priority than the existing memory transaction, the transactional memory access request is a transactional load request, and the target address is within a store footprint of the existing memory transaction;
• wherein the transactional memory circuit is further configured to increase a priority of a memory access within the existing memory transaction in response to receipt from the processor core of an indication of a priority of a different nested memory transaction enclosed within the existing memory transaction.