Anticipated prefetching for a parent core in a multi-core chip

A computer system for prefetching data, the system comprising:

• a chip, comprising:
• a scout core;
• a parent core coupled to the scout;
• and
• a shared cache that is common between the scout core and the parent core, the system configured to perform a method comprising:
• determining that a program executed by the parent core requires content stored in the shared cache;
• sending, from the parent core to the scout core, a fetch table address determined by the parent core via a message passing bus based on determining that content in the shared cache is required, wherein the fetch table address determined by the parent core during compile time and the fetch table address indicates a location of a fetch table;
• receiving, by the scout core, the fetch table address;
• accessing the fetch table by the scout core, the fetch table indicating how many of pieces of content are to be fetched by the scout core and a location of the pieces of content, the accessing in response to the receiving;
• fetching the pieces of content indicated by the fetch table, the fetching by the scout core and in response to the accessing;
• and
• returning the fetched pieces of content to the parent core via the shared cache.