Loading values from a value vector into subregisters of a single instruction multiple data register

A processor that, within the processor, loads values from a vector of values into a series of subregisters of a SIMD register:

• wherein values within the vector of values are contiguous;
• wherein each value in the vector of values is represented by a fixed number of bits;
• wherein the fixed number of bits used to represent every value in the vector of values is the same;
• wherein the processor is configured to respond to one or more instructions by:
• based on the one or more instructions, subdividing the SIMD register into the series of subregisters;
• wherein each subregister in the series of subregisters holds a greater number of bits than the fixed number of bits;
• loading each subregister, of the series of subregisters, with a corresponding portion of the vector of values;
• wherein loading each subregister includes loading the same portion of the vector of values into both a first subregister and a second subregister of the series of subregisters;
• wherein the portion of the vector of values that is loaded into both the first subregister and the second subregister includes both a first value and a second value;
• after loading each subregister with the corresponding portion of the vector of values, performing a plurality of subregister shifting operations;
• wherein the plurality of subregister shifting operations includes a first subregister shifting operation that shifts, by a first amount, the first subregister of the series of subregisters;
• wherein the plurality of subregister shifting operations includes a second subregister shifting operation that shifts, by a second amount, the second subregister of the series of subregisters;
• wherein the first amount is different than the second amount;
• wherein the plurality of subregister shifting operations causes one of:
• the first value to be aligned, in the first subregister, with a left boundary of the first subregister and the second value to be aligned, in the second subregister, with a left boundary of the second subregister,
• the first value to be aligned, in the first subregister, with a right boundary of the first subregister and the second value to be aligned, in the second subregister, with a right boundary of the second subregister, or
• the first value and the second value to be byte-aligned;
• and
• setting to zero all bits in the first subregister other than bits storing the first value;
• and
• setting to zero all bits in the second subregister other than bits storing the second value.