Super multiply add (super MADD) instructions with three scalar terms

#This patent application is a U.S. National Phase Application under 35 U.S.C. §371 of International Application No. PCT/US2011/067096, filed Dec. 23, 2011, entitled SUPER MULTIPLY ADD (SUPER MADD) INSTRUCTION.

#The field of invention relates to computing systems generally, and, more specifically, to a super multiple add instruction with three scalar terms.

#FIG. 1 shows a high level diagram of a processing core 100 implemented with 0.

#The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements and in which:

#FIG. 1 shows a processor pipeline;

#FIGS. 2A and 2B compare scalar vs. vector operations;

#FIGS. 3 and 4 depict a method and corresponding logic circuitry for performing a “super” MADD instruction, VPLANE, that performs the operation V1[ ]=(a*V2[ ])+(b*V3[ ])+c, where, V1[ ] is the resultant vector, V2[ ] and V3[ ] are input vectors and a, b and c are scalars 401. As observed in FIG. 3, the execution unit that performs the operation may adopt an instruction format technology that takes the form of VPLANE R1; R2; R3; R4/M. In so doing, the instruction format separately refers to: i) a destination register address R1 to store the result V1[ ]; ii) two separate input operand register addresses R2 and R3 to respectively store input operands V2[ ], V3[ ]; and, iii) a third input operand address R3 or M that defines a register or memory storage location where each of the scalars a, b, c are found. Alternatively, the instruction format may take the form of VPLANE R1; R2; R3/M where R1 holds one of the source operands and the destination. A more formal format for the VPLANE instruction may include a write mask (e.g., VPLANE R1; k; R2; R3; R4/M where k corresponds to the mask vector). In a further embodiment, only a write mask (layer 105 of FIG. 1) is employed as part of the architecture. For simplicity the remainder of this description will mostly refer to the VPLANE R1; R2; R3; R4/M format.

#In an embodiment, each of references R1; R2; R3 and R4 correspond to locations in vector register space 107 of FIG. 1. Similarly, M corresponds to a location in memory where vector values are stored. In an embodiment, the scalar values a, b, c are called from storage space R4/M that is nominally used to store vectors. That is, the VPLANE instruction has five input operands (V2[ ], V3[ ], a, b and c) but consumes only three input data sources (e.g., three registers or two registers and a memory location).

#In order to accomplish the compaction of input information, as observed in FIG. 3, the scalars a, b, c are “packed” into a same input data structure to effectively provide the three scalars from a single source. Notably, the “packed” or vector-like data structure that contains the scalar values a, b, c in R4/M does not necessarily have the same vector size as the other vectors called out by the instruction. Thus, unlike typical vector instructions where each input operand is a vector of same size, the structure of the VPLANE instruction entertains the possibility that one group of input operands V2[ ], V3[ ] will be a vector of a first size (any vector size supported by the machine) while another input operand is essentially a vector of a different, second size (three).