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US 9,792,087 B2Granted
System and method for a floating-point format for digital signal processors
AssigneeFuturewei Technologies, Inc.
InventorsYuanbin Guo, Tong Sun, Weizhong Chen
Life of this patent
Estimating the term…
Abstract
An embodiment of a system and method for performing a numerical operation on input data in a hybrid floating-point format includes representing input data as a sign bit, exponent bits, and mantissa bits. The exponent bits are represented as an unsigned integer including an exponent bias, and a signed numerical value of zero is represented as a first reserved combination of the mantissa bits and the exponent bits. Each of all other combinations of the mantissa bits and the exponent bits represents a real finite non-zero number. The mantissa bits are operated on with a “one” bit before a radix point for the all other combinations of the mantissa bits and the exponent bits.
Claims18
An apparatus comprising:
- a memory;
- and
- a processor coupled to the memory, the processor configured to receive a multiple-input multiple output (MIMO) wireless baseband signal comprising input data having a sign bit, exponent bits, and mantissa bits, the processor comprising a hardware floating-point unit configured to perform a numerical operation on the input data in a 16-bit half-precision floating-point format,
- wherein the exponent bits comprise an unsigned integer with an implied bias 16 providing symmetry in a 1/x reciprocal operation,
- wherein a representation of a signed numerical value of zero comprises a first reserved combination of the mantissa bits and the exponent bits, wherein each of all other combinations of the mantissa bits and the exponent bits represents a real finite non-zero number,
- wherein the mantissa bits are preceded by a bit “1” before a radix point for the all other combinations of the mantissa bits and the exponent bits;
- and
- wherein the numerical operation comprises a multiplication or a division operation;
- wherein the hardware floating-point unit comprises dedicated tail bit cut-off-only logic to cut off excess tail bits of an intermediate mantissa result without rounding the intermediate mantissa result;
- wherein the hardware floating-point unit is further configured to produce from the numerical operation a result that is always either zero or a real finite non-zero number;
- and
- wherein the processor is further configured to use the result of the numerical operation performed by the hardware floating-point unit in processing the MIMO wireless baseband signal.
9 more elements
A method of performing a numerical operation on input data in a 16-bit half-precision floating-point format, the method comprising:
- receiving a multiple-input multiple output (MIMO) wireless baseband signal comprising input data having a sign bit, exponent bits, and mantissa bits;
- representing, by a hardware floating-point unit in accordance with the 16-bit half-precision floating-point format, the exponent bits as an unsigned integer with an implied bias 16 providing symmetry in a 1/x reciprocal operation;
- representing, by the hardware floating-point unit, a signed numerical value of zero as a first reserved combination of the mantissa bits and the exponent bits, wherein each of all other combinations of the mantissa bits and the exponent bits represents a real finite non-zero number;
- numerically operating, by the hardware floating-point unit, on the mantissa bits with a bit “1” before a radix point for the all other combinations of the mantissa bits and the exponent bits to produce a result, the numerical operation comprising a multiplication or a division operation;
- cutting off excess tail bits of an intermediate mantissa result, without rounding the intermediate mantissa result, in the hardware floating-point unit with dedicated tail bit cut-off-only logic;
- producing, by the hardware floating-point unit from the numerical operation, a result that is always either zero or a real finite non-zero number;
- and
- using the result in processing the MIMO wireless baseband signal.
5 more elements
An apparatus comprising:
- a memory;
- and
- a processor coupled to the memory, the processor configured to receive a wireless baseband signal comprising input data having a sign bit, exponent bits, and mantissa bits, the processor comprising a hardware floating-point unit configured to perform a numerical operation on the input data in a 28-bit full-precision floating-point format,
- wherein the exponent bits comprise an unsigned integer including an exponent bias, and wherein the exponent bias is 64,
- wherein a representation of a signed numerical value of zero comprises a first reserved combination of the mantissa bits and the exponent bits, wherein each of all other combinations of the mantissa bits and the exponent bits represents a real finite non-zero number,
- wherein the mantissa bits are preceded by a bit “1” before a radix point for the all other combinations of the mantissa bits and the exponent bits;
- and
- wherein the numerical operation comprises a multiplication or a division operation;
- wherein the hardware floating-point unit comprises dedicated tail bit cut-off-only logic to cut off excess tail bits of an intermediate mantissa result without rounding the intermediate mantissa result;
- wherein the hardware floating-point unit is further configured to produce from the numerical operation a result that is always either zero or a real finite non-zero number;
- and
- wherein the processor is further configured to use the result of the numerical operation performed by the hardware floating-point unit in processing the wireless baseband signal.
9 more elements
A method of performing a numerical operation on input data in a 28-bit full-precision floating-point format, the method comprising:
- receiving a wireless baseband signal comprising input data having a sign bit, exponent bits, and mantissa bits;
- representing, by a hardware floating-point unit, the exponent bits as an unsigned integer including an exponent bias, wherein the exponent bias is 64 in accordance with the 28-bit full-precision floating-point format;
- representing, by the hardware floating-point unit, a signed numerical value of zero as a first reserved combination of the mantissa bits and the exponent bits, wherein each of all other combinations of the mantissa bits and the exponent bits represents a real finite non-zero number;
- numerically operating, by the hardware floating-point unit, on the mantissa bits with a bit “1” before a radix point for the all other combinations of the mantissa bits and the exponent bits to produce a result, the numerical operation comprising a multiplication or a division operation;
- cutting off excess tail bits of an intermediate mantissa result, without rounding the intermediate mantissa result, in the hardware floating-point unit with dedicated tail bit cut-off-only logic;
- producing, by the hardware floating-point unit from the numerical operation, a result that is always either zero or a real finite non-zero number;
- and
- using the result in processing the wireless baseband signal.
5 more elements
Dependencies are inferred from the claim text.