Acceleration of memory access

A memory unit, comprising:

• a memory;
• a programmable circuit that is a circuit configurable in accordance with one or more programs;
• and
• an instruction handler configured to be in communication with the programmable circuit, wherein the instruction handler is configured to:
• receive, from a virtual machine being executed by a processor, a request to access the memory in the memory unit, wherein:
• the request specifies a program among the one or more programs,
• the program includes one or more instructions to configure circuitry of the programmable circuit to perform one or more operations on data stored in the memory, and
• the program is associated with the virtual machine being executed by the processor;
• and
• in response to the receipt of the request, configure the circuitry of the programmable circuit, in accordance with the program, to perform the one or more operations on the data stored in the memory, wherein the programmable circuit includes one or more of a field-programmable logic array (FPGA), a semi-programmable application-specific integrated circuit (ASIC), or a digital signal processor, and wherein the programmable circuit is effective to:
• perform the one or more operations on the data stored in the memory in accordance with the program.

A method for a memory unit that includes a memory and a programmable circuit, the memory unit being configured in communication with two or more virtual machines executable by a processor, the method for the memory unit comprising:

• receiving, from a first virtual machine executed by the processor, a first request at the memory unit, wherein:
• the first request is to access the memory in the memory unit,
• the first request specifies a first program,
• the first program includes a first instruction to configure circuitry of the programmable circuit to perform a first set of one or more operations on data stored in the memory included in the memory unit,
• the programmable circuit includes a circuit configurable in accordance with one or more programs,
• the one or more programs include the first program, and
• the first program is associated with the first virtual machine;
• in response to receiving the first request, configuring the circuitry of the programmable circuit, in accordance with the first program, to perform the first set of one or more operations on the data stored in the memory included in the memory unit, wherein the programmable circuit includes one or more of a field-programmable logic array (FPGA), a semi-programmable application-specific integrated circuit (ASIC), or a digital signal processor;
• operating the programmable circuit to perform the first set of one or more operations on the data stored in the memory in accordance with the first program;
• receiving, from a second virtual machine executed by the processor, a second request at the memory unit, wherein:
• the second request specifies a second program,
• the second program includes a second instruction to configure the circuitry of the programmable circuit to perform a second set of one or more operations on the data stored in the memory included in the memory unit,
• the one or more programs include the second program, and
• the second program is associated with the second virtual machine;
• configuring the circuitry of the programmable circuit, in accordance with the second program, to perform the second set of one or more operations on the data stored in the memory included in the memory unit;
• and
• operating the programmable circuit to perform the second set of one or more operations on the data stored in the memory in accordance with the second program.

A computer program product, comprising computer-readable instructions stored in non-transitory computer-readable media, the computer-readable instructions, operable in response to execution by a processor, to:

• detect, from the processor, a request to access a memory in a memory unit, wherein:
• the request specifies a program,
• the program includes one or more instructions to configure circuitry of a programmable circuit of the memory unit to perform one or more operations on data stored in the memory in the memory unit,
• the programmable circuit includes a circuit configurable in accordance with one or more programs,
• the programmable circuit includes one or more of a field-programmable logic array (FPGA), a semi-programmable application-specific integrated circuit (ASIC), or a digital signal processor,
• the one or more programs include the program, and
• the program is associated with a virtual machine being executed by the processor;
• in response to the detection of the request, configure the circuitry of the programmable circuit, in accordance with the program, to perform the one or more operations on the data stored in the memory in the memory unit;
• and
• operate the programmable circuit to perform the one or more operations on the data stored in the memory in accordance with the program.