Rate scalable IO interface with zero stand-by power and fast start-up
AssigneeIntel Corporation
InventorsStephen R. Mooney, Howard L. Heck, James E. Jaussi, Bryan K. Casper
Life of this patent
Estimating the term…
Abstract
Systems and methods of interconnecting devices may include an input/output (IO) interface having one or more clock circuits, a power supply coupled to the one or more clock circuits, and logic to receive a rate adjustment command at the IO interface. The logic may also be configured to adjust a data rate of the IO interface in response to the rate adjustment command, and to adjust an output voltage of the power supply in response to the rate adjustment command.
Claims34
A host platform comprising:
- a power supply,
- a host device to issue a rate adjustment command,
- an input/output (IO) interface including a datapath section having one or more clock circuits coupled to the power supply,
- a multiplexer,
- an IO controller,
- a voltage regulator associated with the one or more clock circuits of the IO interface, and logic to,
- receive the rate adjustment command at the IO interface,
- adjust a data rate of the IO interface in response to the rate adjustment command, and
- adjust an output voltage of the power supply in response to the rate adjustment command,
- wherein the output voltage is adjusted by activating or deactivating the voltage regulator, and wherein upon receipt of a restart command, the voltage regulator is activated by the IO controller and the multiplexer uses a common clock to transfer data from the IO interface until a lock condition is detected.
An input/output (IO) interface comprising:
- a datapath section including one or more clock circuits,
- a multiplexer,
- a power supply coupled to the one or more clock circuits, and
- logic to,
- receive a rate adjustment command at the IO interface,
- adjust a data rate of the IO interface in response to the rate adjustment command, and
- adjust an output voltage of the power supply in response to the rate adjustment command,
- wherein the output voltage is adjusted by activating or deactivating a voltage regulator associated with the one or more clock circuits of the IO interface, and wherein, upon receipt of a restart command, the voltage regulator is activated based on receipt of a restart command and the multiplexer uses a common clock to transfer data from the IO interface until a lock condition is detected.
A computer implemented method comprising:
- receiving a rate adjustment command from a host device at an input/output (IO) interface;
- adjusting a data rate of the IO interface in response to the rate adjustment command;
- and
- adjusting an output voltage of a power supply associated with one or more clock circuits of the IO interface in response to the rate adjustment command;
- wherein the output voltage is adjusted by activating or deactivating a voltage regulator associated with one or more clock circuits of the IO interface, and wherein, upon receipt of a restart command, the voltage regulator is activated and a common clock is used to transfer data from the IO interface until a lock condition is detected.
A non-transitory computer readable storage medium comprising a set of instructions which, if executed by a processor, cause an input/output (IO) interface to:
- receive a rate adjustment command from a host device at the IO interface;
- adjust a data rate of the IO interface in response to the rate adjustment command;
- and
- adjust an output voltage of a power supply associated with one or more clock circuits of the IO interface in response to the rate adjustment commands;
- wherein the output voltage is adjusted by activating or deactivating a voltage regulator associated with one or more clock circuits of the IO interface, and wherein, upon receipt of a restart command, the voltage regulator is activated and a common clock is used to transfer data from the IO interface until a lock condition is detected.
Dependencies are inferred from the claim text.