Fast digital to time converter linearity calibration to improve clock jitter performance

An apparatus comprising:

• a digital-to-time converter (DTC) to generate output signals with phase offsets set by an input value;
• a time-to-digital converter (TDC) operatively coupled to the DTC, wherein the TDC has a lower resolution than the DTC;
• and
• a processing component operatively coupled to the DTC and the TDC, the processing component to:
• determine a first DTC input value corresponding to a first TDC threshold;
• determine a second DTC input value corresponding to a second TDC threshold;
• and
• generate a portion of a calibration function based on the first DTC input value and the second DTC input value, wherein the calibration function estimates DTC input values corresponding to phase offsets different from the first TDC threshold and the second TDC threshold.

A method comprising:

• determining a first input value for a digital-to-time converter (DTC) that corresponds to a first threshold of a time-to-digital converter (TDC), wherein the DTC has a higher resolution than the TDC;
• determining a second input value for the DTC corresponding to a second threshold of the TDC;
• and
• generating, by a processing component, a portion of a calibration function based on the first input value and the second input value, wherein the calibration function estimates input values corresponding to a phase offsets that are different from the first threshold or the second threshold.