Method and apparatus for low latency communication in an automatic testing system
AssigneeTeradyne, Inc.
InventorsThien D. Nguyen, George W. Conner
Life of this patent
Estimating the term…
Loading patent…
AssigneeTeradyne, Inc.
InventorsThien D. Nguyen, George W. Conner
Estimating the term…
According to some aspects, a system and method for processing messages in a plurality of successive cycles is provided. One such system may include a plurality of first circuits, each first circuit configured to output a message, the plurality of first circuits configured to operate synchronously, a first plurality of buffers, each buffer associated with a respective first circuit and configured to store a message output by the respective first circuit, a communication path configured to receive the plurality of messages from the buffers and to perform aggregation of the messages, thereby generating an aggregated indication, and one or more second circuits. The one or more second circuits are configured to operate synchronously and to receive the aggregated indication, wherein buffers of the first plurality of buffers are configured to store messages from respective first circuits for different times.
A system for processing flags that indicate a state of a device under test, the flags being processed in a plurality of successive cycles, the system comprising:
An interface circuit for an automatic test system in which a communication path carries flags that indicate a state of a device under test, comprising:
Dependencies are inferred from the claim text.