Customer-transparent logic redundancy for improved yield

An integrated circuit structure comprising:

• a plurality of latch structures including original latch structures comprising a first input configured to receive data on a first scan path and a plurality of repair latch structures which are respectively duplicates of each respective original latch within the plurality of latch structures;
• and
• a plurality of logic structures including original logic structures comprises a first input configured to receive data on the first scan path and a plurality of repair logic structures which are respectively duplicates of each respective original logic structure within the plurality of logic structures, such that a two-fold library of latches and logic is provided for one or more scan chains of the integrated circuit structure,
• wherein the plurality of latch structures is configured to provide an output indicative of whether all of the original latch structures are not defective in response to a test scan of the plurality of latch structures,
• wherein, when all of the original latch structures pass the test scan, the plurality of logic structures is configured to provide an output indicative of whether all of the original logic structures pass a logic test, different than the test scan, and
• wherein, when one of the original latch structures does not pass the test scan, the plurality of latch structures is configured so that one of the repair latch structures is substituted for a defective original latch structure as a repair so that the logic test is carried out on the plurality of logic structures.