Integrated circuit having receiver jitter tolerance (“JTOL”) measurement
AssigneeRambus Inc.
InventorsHae-Chang Lee, Jaeha Kim, Brian Liebowitz
Life of this patent
Estimating the term…
Abstract
An integrated circuit capable of on-chip jitter tolerance measurement includes a jitter generator circuit to produce a controlled amount of jitter that is injected into at least one clock signal, and a receive circuit to sample an input signal according to the at least one clock signal. The sampled data values output from the receiver are used to evaluate the integrated circuit's jitter tolerance.
Claims20
An integrated circuit to couple to a conductive signal path and to receive an incoming data signal sent by an external transmitter circuit via the conductive signal path, the integrated circuit comprising:
- a receiver to sample the incoming data signal at sampling times, to generate data samples;
- and
- circuitry to provide a clock signal dependent on phase information sent by the external transmitter circuit;
- wherein the integrated circuit has two modes, including
- a normal mode of operation in which a sampling clock is provided to the receiver and used to trigger sampling at the sampling times to generate the data signals, the sampling clock tracking phase of the clock signal, and
- a test mode of operation in which circuitry is to controllably vary the sampling times relative to the clock signal, and in which data samples generated from the varied sampling times are used to evaluate performance of the integrated circuit in the presence of added noise.
An integrated circuit to couple to a conductive signal path and to receive an incoming data signal sent by an external transmitter circuit via the conductive signal path, the integrated circuit comprising:
- a receiver to sample the incoming data signal at sampling times, to generate data samples;
- and
- circuitry to provide a clock signal dependent on phase information sent by the external transmitter circuit, the phase information being embedded in the incoming data signal, the circuitry to provide to generate the clock signal as a recovered clock signal having a phase that tracks the timing of logic level transitions carried by the incoming data signal;
- wherein the integrated circuit has two modes, including
- a normal mode of operation in which a sampling clock is provided to the receiver and used to trigger sampling at the sampling times to generate the data signals, the sampling clock tracking phase of the clock signal, and
- a test mode of operation in which circuitry is to controllably vary the sampling times relative to the clock signal, and in which data samples generated from the varied sampling times are used to evaluate performance of the integrated circuit in the presence of added noise.
An integrated circuit to couple to conductive signal paths and to receive respective incoming data signals via the conductive signal paths from by an external transmitter circuit, the integrated circuit comprising:
- receivers corresponding to the conductive signal paths, each receiver to sample a respective one of the incoming data signal at sampling times, to generate respective data samples;
- and
- circuitry to provide a clock signal dependent on phase information sent by the external transmitter circuit;
- wherein the integrated circuit has two modes, including
- a normal mode of operation in which a sampling clock is provided to each of the receivers and used to trigger sampling at the sampling times to generate the respective data signals, the sampling clock tracking phase of the clock signal, and
- a test mode of operation in which circuitry is to controllably vary the sampling times relative to the clock signal, and in which data samples generated from the varied sampling times are used to evaluate performance of the integrated circuit in the presence of added noise.
Dependencies are inferred from the claim text.