Faster and more efficient different precision sum of absolute differences for dynamically configurable block searches for motion estimation

A method of digital signal processing comprising the steps of:

• storing data in a plurality of data registers of a data register file, each data register designated by a corresponding register number;
• storing instructions, each instruction specifying a data processing operation and at least one data operand by register number, at least one instruction specifying a sum of absolute differences (SAD) operation;
• sequentially recalling said stored instructions;
• decoding said specified data processing operation and said specified at least one operand of each recalled instruction;
• performing data processing operations upon at least one operand corresponding to a decoded instruction, said data processing operations including, in response to an instruction specifying a sum of absolute differences (SAD) operation, performing a sum of absolute differences (SAD) operation comprising two sets of a plurality of rows, each row producing a SAD output and including
• performing a plurality of absolute value difference operations employing a plurality of absolute difference units, each absolute difference unit having a first input receiving candidate pixel data packed within data stored in a first instruction specified data register and a second input receiving corresponding reference pixel data packed within data stored in a second instruction specified data register, an output generating a corresponding output, including
• forming an arithmetic inversion of a value of said first input,
• forming an arithmetic sum of values of said first input and said second input and a carry output,
• conditionally forming an arithmetic inversion of a value of said arithmetic sum dependent upon a value of said carry output, and
• logically ANDing said output of said conditional second inverting and a corresponding mask input,
• summing said outputs of each absolute value difference operation in each row forming a row sum output via a row summer connected to said output of each absolute difference unit in said row, and
• wherein said candidate pixels are offset relative to said reference pixels by one pixel for each succeeding row in a set of rows;
• wherein said sum of absolute differences (SAD) operation includes a first mode forming 2M SADs from N bit pixel data and a second mode forming M SADs from 2N bit pixel data, said first mode and said second mode selected by carry chain control in said plurality of absolute value difference units and said row summers;
• and
• wherein a first set of a plurality of rows operates on pixel data in a first half of said first instruction specified data register and a second set of a plurality of rows operates on pixel data in a second half of said first instruction specified data register.