Delay circuit
AssigneeSK hynix Inc.
InventorsSung-Eun Lee, Kyung-Hoon Kim, Myeong-Jae Park, Woo-Yeol Shin, Han-Kyu Chi, Yong-Ju Kim
Life of this patent
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Abstract
A delay circuit includes: a plurality of delay units that are serially coupled with each other in a form of loop and sequentially delay an input signal of the delay circuit; an input control unit that selects a delay unit to receive the input signal of the delay circuit among the plurality of the delay units; and an output control unit that controls an output signal of a predetermined delay unit among the plurality of the delay units to be outputted as an output signal of the delay circuit, when the output signal of the predetermined delay unit is enabled N times, where N is an integer equal to or greater than 0.
Claims18
A delay circuit comprising:
- a plurality of delay units that are serially coupled to each other in a loop suitable for sequentially delaying an input signal of the delay circuit;
- an input control unit suitable for selecting a delay unit to receive the input signal of the delay circuit among the plurality of the delay units;
- and
- an output control unit suitable for controlling an output signal of a preset delay unit among the plurality of the delay units to be outputted as an output signal of the delay circuit, when the output signal of the preset delay unit is enabled N times, where N is an integer equal to or greater than 0,
- wherein the input control unit selects a delay unit to receive the input signal of the delay circuit among the plurality of the delay units in response to a first bit group of a delay control code.
A delay circuit comprising:
- first to Kth delay units that are serially coupled to each other in a loop for sequentially delaying an input signal of the delay circuit, where K is an integer equal to or greater than 2;
- and
- an output control unit suitable for controlling an output signal of an Lth delay unit to be outputted as an output signal of the delay circuit, when the output signal of the Lth delay unit is enabled in a predetermined number of times, where L is an integer equal to or greater than 1 and equal to or smaller than K,
- wherein an Mth delay unit receives the input signal of the delay circuit among the first to Kth delay units, where M is an integer equal to or greater than 1 and equal to or smaller than K,
- wherein each of the first to Kth delay units includes:
- a first selector suitable for selecting one of an output signal of a preceding delay unit and the input signal of the delay circuit as an input signal of a corresponding delay unit;
- a delay line suitable for delaying a signal selected by the first selector;
- and
- a second selector suitable for outputting a signal delayed by the delay line, as an output signal of the corresponding delay unit, to one of a subsequent delay unit and an exit path from which the output signal of the delay circuit is outputted.
A delay circuit comprising:
- a plurality of delay units serially coupled to each other in a ring shape and sequentially delay an input signal of the delay circuit;
- an input control unit suitable for receiving the input signal of the delay circuit to generate a plurality of input control signals each of which is assigned to each of the delay units, in response to a first bit group of a delay control code;
- and
- an output control unit suitable for generating an output control signal in response to a second bit group of the delay control code and an output signal of a preset delay unit selected from the delay units,
- wherein each delay unit receives one of an output signal of a preceding delay unit and the input signal of the delay circuit in response to an assigned input control signal, and
- wherein the preset delay unit outputs the output signal thereof to one of a subsequent delay unit and an exit path from which an output signal of the delay circuit is outputted, in response to the output control signal.
Dependencies are inferred from the claim text.