Resource-saving circuit structures for deeply pipelined systolic finite impulse response filters

Circuitry accepting a data input and an enable input and generating a finite impulse response output based on the data input, the circuitry comprising:

• an input stage circuit including an input register;
• an enable register that receives the enable input and generates a delayed enable signal;
• an intermediate stage circuit that is coupled to the input stage circuit including:
• first and second systolic registers that are operated without any enable connection at the steady state of the circuitry,
• a third systolic register sequentially connected to the first systolic register, wherein the third systolic register is connected to the enable register to accept the delayed enable signal,
• a first multiplier connected in series with the first and third systolic registers;
• a second multiplier connected in series with the second systolic register;
• and
• an output stage circuit operatively connected to the intermediate stage circuit, including:
• an adder circuit including a single adder, or a pair of adders without any physical element separating the pair of adders.

A pipelined systolic finite impulse response (FIR) filter, comprising:

• an input stage circuit including an input register, wherein
• the input register accepts an enable input;
• an enable delay register that accepts the enable input and generates a delayed enable signal;
• a FIR calculation circuit that is coupled to the input stage circuit, including:
• a first systolic register that is operated without any enable connection at the steady state of the circuitry,
• a second systolic register sequentially connected to the first systolic register, wherein the second systolic register is connected to the enable delay register to accept the delayed enable signal, and
• a multiplier connected in series with the first and second systolic registers;
• an output stage circuit, including an adder that calculates an output sum;
• and
• a plurality of pipeline registers to pipeline part of an operation of the FIR calculation circuit or the adder, wherein
• each pipeline stage of the pipelined systolic FIR filter has a separate enable register without fanning out the enable input for each pipeline stage.

A method for operating a pipelined systolic finite impulse response (FIR) filter, comprising:

• receiving, at an input register, a data input signal and an enable input signal, wherein
• the input register generates a delayed data input signal;
• receiving, at an enable register, the enable input signal, wherein the enable register generates a delayed enable signal;
• transmitting the delayed data input signal to a first systolic register operatively connected to the input register, wherein
• the first systolic register is operated without any enable connection;
• transmitting a first systolic register output from the first systolic register to a second systolic register, wherein the second systolic register accepts the delayed enable signal from the enable register;
• calculating, at a multiplier, a product value based at least in part on a second systolic register output from the second systolic register;
• and
• generating, at an adder, an output sum based least in part on the product value.