Mismatch correction in differential amplifiers using analog floating gate transistors

A differential amplifier circuit comprising:

• a tail current source, for conducting a tail current from a first reference voltage;
• a first input leg coupled between the current source and a second reference voltage, comprising:
• a first input transistor, having a source/drain path and a gate, the gate receiving a first input voltage;
• and
• a first load device connected in series with the source/drain path of the first input transistor;
• a second input leg coupled in parallel with the first input leg between the current source and a second reference voltage, comprising:
• a second input transistor, having a source/drain path and a gate, the gate receiving a second input voltage;
• and
• a second load device connected in series with the source/drain path of the second input transistor;
• an output circuit, coupled to the first and second input legs, for presenting an output corresponding to a difference between the first and second input voltages;
• a first analog floating gate device, comprising:
• a floating gate electrode;
• a tunnel capacitor, having a plate coupled to a programming node and capacitively coupled to the floating gate electrode;
• a first trim transistor, having a source/drain path connected in parallel with the first load device, the floating gate electrode serving as a gate of the first trim transistor;
• and
• a second trim transistor, having a source/drain path, the floating gate electrode serving as a gate of the second trim transistor;
• a second analog floating gate device, comprising:
• a floating gate electrode;
• a tunnel capacitor, having a plate coupled to a programming node and capacitively coupled to the floating gate electrode;
• a third trim transistor, having a source/drain path connected in parallel with the second load device, the floating gate electrode serving as a gate of the third trim transistor;
• and
• a fourth trim transistor, having a source/drain path, the floating gate electrode serving as a gate of the fourth trim transistor;
• and
• a tail current mirror comprising:
• a first tail transistor having a source/drain path coupled between the first and second reference voltages so as to conduct a current corresponding to currents conducted by the second and fourth trim transistors;
• and
• a second tail transistor having a source/drain path connected between the first reference voltage and the first and second input legs, and a gate coupled to the first tail transistor so that the second tail transistor conducts a current corresponding to the current conducted by the first tail transistor.

A method of trimming an analog differential circuit, the analog differential circuit comprising first and second input legs that each include an input transistor with a gate receiving an input voltage, in series with a load device, a current source producing a tail current applied to the first and second input legs arranged in parallel, and an output circuit presenting an output level responsive to a difference between the input voltages received by the first and second input legs, the method comprising:

• measuring an input offset corresponding to the output level with zero differential in the input voltages applied to the first and second input legs;
• programming a floating gate electrode of a first trim transistor to a first gate voltage, the first trim transistor having a source/drain path connected in parallel with the load device of the first input leg;
• and
• programming a floating gate electrode of a second trim transistor to a second gate voltage, the second trim transistor having a source/drain path connected in parallel with the load device of the second input leg, and the second gate voltage differing from the first gate voltage by an amount corresponding to the measured input offset;
• wherein at least one of the first and second gate voltages is above the threshold voltage of its trim transistor.