Method and apparatus for low-complexity quasi-reduced state soft-output equalizer
AssigneeHuawei Technologies Co., Ltd.
InventorsJeebak Mitra, Zhuhong Zhang
Life of this patent
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Abstract
Quasi-reduced state trellis equalization techniques achieve low-latency inter-symbol interference (ISI) equalization by selecting a subset of accumulated path metrics (APMs) for a leading symbol to propagate over a trellis to candidate states of a trailing symbol. This simplifies the computation of APMs for candidate states of the trailing symbol. Thereafter, APMs for candidate states of the trailing symbol are computed based on the subset of APMs for the leading symbol that were propagated over the trellis. Propagating fewer than all APMs for the leading symbol to the trailing symbol reduces the complexity of APM computation at the trailing symbol.
Claims20
A method for staggered processing of modulated symbols, the method comprising:
- dividing a sequence of modulated symbols into a sequence of blocks, wherein the sequence of blocks includes a leading block immediately preceding a trailing block;
- processing, via parallel processors, a first set of staggered blocks during a first processing period, the first set of staggered blocks including the leading block and excluding the trailing block;
- and
- processing, via the parallel processors, a second set of staggered blocks during a second processing period, the second set of staggered blocks including the trailing block and excluding the leading block, wherein a single one of the parallel processors processes both the leading block during the first processing period and the trailing block during the second processing period.
An apparatus comprising:
- a processor;
- and
- a computer readable storage medium storing programming for execution by the processor, the programming including instructions to:
- divide a sequence of modulated symbols into a sequence of blocks, wherein the sequence of blocks includes a leading block immediately preceding a trailing block;
- process, via parallel processors, a first set of staggered blocks during a first processing period, the first set of staggered blocks including the leading block and excluding the trailing block;
- and
- process, via the parallel processors, a second set of staggered blocks during a second processing period, the second set of staggered blocks including the trailing block and excluding the leading block, wherein a single one of the parallel processors processes both the leading block during the first processing period and the trailing block during the second processing period.
A computer program product comprising a non-transitory computer readable storage medium storing programming, the programming including instructions to:
- divide a sequence of modulated symbols into a sequence of blocks, wherein the sequence of blocks includes a leading block immediately preceding a trailing block;
- process, via parallel processors, a first set of staggered blocks during a first processing period, the first set of staggered blocks including the leading block and excluding the trailing block;
- and
- process, via the parallel processors, a second set of staggered blocks during a second processing period, the second set of staggered blocks including the trailing block and excluding the leading block, wherein a single one of the parallel processors processes both the leading block during the first processing period and the trailing block during the second processing period.
Dependencies are inferred from the claim text.